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Interactive Debug of SoCs with Multiple Clocks
May/June 2011 (vol. 28 no. 3)
pp. 44-51
B Vermeulen, NXP Semicond., Netherlands
K Goossens, Electr. Eng. Dept., Eindhoven Univ. of Technol., Eindhoven, Netherlands
Systems with elaborate multiple clock distributions are a necessity, and the authors address the postfabrication debug of such multiclock systems. Solutions, based on the authors' communication-centric debug approach, are presented that achieve a consistent snapshot of the system state and force the erroneous state in the face of nondeterminism.

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Index Terms:
system-on-chip,clocks,electronic engineering computing,interactive systems,communication centric debug approach,interactive SoC debugging,multiple clock distribution,postfabrication debug,System-on-a-chip,IP networks,Debugging,Monitoring,Synchronization,Multicore processing,debug abstraction techniques,design and test,embedded SoC,network on chip,multiple clocks,silicon validation,silicon debug,software debug,consistent global state dumps,handshake signals,communication-centric debug
Citation:
B Vermeulen, K Goossens, "Interactive Debug of SoCs with Multiple Clocks," IEEE Design & Test of Computers, vol. 28, no. 3, pp. 44-51, May-June 2011, doi:10.1109/MDT.2011.42
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