This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
On MPSoC Software Execution at the Transaction Level
May/June 2011 (vol. 28 no. 3)
pp. 32-43
Frédéric Pétrot, Grenoble Institute of Technology
Patrice Gerin, Kalray
Marius Gligor, Grenoble Institute of Technology
Mian-Muhammed Hamayun, Grenoble Institute of Technology
Hao Shen, Grenoble Institute of Technology

Editor's note:

This article presents a wide variety of techniques for realizing transaction-level models of the increasingly large-scale multiprocessor systems on chip. It describes how such models of hardware allow subsequent software integration and system performance evaluation.

—Zeljko Zilic, McGill University

1. F. Ghenassia and A. Clouard, "TLM: An Overview and Brief History," Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems, F. Ghenassia ed., Springer, 2005, pp. 1-22.
2. M.V. Wilkes, "The Growth of Interest in Microprogramming: A Literature Survey," ACM Computing Surveys, vol. 1, no. 3, 1969, pp. 139-145.
3. K. Popovici, and A. Jerraya, "Hardware Abstraction Layer—Introduction and Overview," Hardware- Dependent Software: Principles and Practice, W. Ecker, W. Müller, and R. Dömer eds., Springer, 2009, pp. 67-94.
4. J.R. Bell,, "Hardware Abstraction Layer: Introduction and Overview," Comm. ACM, vol. 16, no. 6, 1973, pp. 370-372.
5. L.P. Deutsch and A.M. Schiffman, "Efficient Implementation of the Smalltalk-80 System," Proc. 11th ACM SIGACT-SIGPLAN Symp. Principles of Programming Languages, ACM Press, 1984, pp. 297-302.
6. F. Bellard, "QEMU: A Fast and Portable Dynamic Translator," Proc. USENIX Ann. Technical Conf. (ATEC 05), Usenix Assoc., 2005, pp. 41-46.
7. M. Monton, J. Carrabina, and M. Burton, "Mixed Simulation Kernels for High Performance Virtual Platforms," Proc. Forum Specification and Design Languages (FDL 09), IEEE Press, 2009.
8. B. Cmelik and D. Keppel, "Shade: A Fast Instruction-Set Simulator for Execution Profiling," Proc. ACM SIGMETRICS Conf. Measurement and Modeling of Computer Systems, ACM Press, 1994, pp. 128-137.
9. R.K. Gupta, C.N. Coelho Jr., and G. De Micheli, "Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components," Proc. 29th Design Automation Conf. (DAC 92), IEEE CS Press, 1992, pp. 225-230.
10. A. Gerstlauer, H. Yu, and D. Gajski, "RTOS Modeling for System Level Design," Proc. Design, Automation and Test in Europe Conf. (DATE 03), vol. 1, IEEE CS Press, 2003, pp. 130-135.
11. H. Posadas and E. Villar, "Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co- simulation," Analysis, Architectures and Modelling of Embedded Systems: IFIP Advances in Information and Comm. Technology, vol. 310, no. 9, 2009, pp. 12-23.
12. Z. Wang and A. Herkersdorf, "An Efficient Approach for System-Level Timing Simulation of Compiler-Optimized Embedded Software," Proc. 46th Design Automation Conf. (DAC 09), ACM Press, 2009, pp. 220-225.

Index Terms:
design and test, hardware-software simulation, MPSoC modeling, software simulation, performance estimation, code interpretation, native simulation
Citation:
Frédéric Pétrot, Nicolas Fournel, Patrice Gerin, Marius Gligor, Mian-Muhammed Hamayun, Hao Shen, "On MPSoC Software Execution at the Transaction Level," IEEE Design & Test of Computers, vol. 28, no. 3, pp. 32-43, May-June 2011, doi:10.1109/MDT.2010.118
Usage of this product signifies your acceptance of the Terms of Use.