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Multicore Simulation of Transaction-Level Models Using the SoC Environment
May/June 2011 (vol. 28 no. 3)
pp. 20-31
Weiwei Chen, Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, CA, USA
Xu Han, Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, CA, USA
R Doemer, Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, CA, USA
Editor's note: To address the limitations of discrete-event simulation engines, this article presents an extension of the SoC simulation kernel to support parallel simulation on multicore hosts. The proposed optimized simulator enables fast validation of large multicore SoC designs by issuing multiple simulation threads simultaneously while ensuring safe synchronization.

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Index Terms:
system-on-chip,multiprocessing systems,multicore hosts,multicore simulation,transaction level models,SoC environment,discrete-event simulation engines,parallel simulation,System-on-a-chip,Computational modeling,Solid modeling,Synchronization,Multicore processing,Parallel processing,Transaction databases,Simulation,JPEG encoder,design and test,ESL design,multicore parallel simulation,SoC environment,SCE,H.264,video decoder
Weiwei Chen, Xu Han, R Doemer, "Multicore Simulation of Transaction-Level Models Using the SoC Environment," IEEE Design & Test of Computers, vol. 28, no. 3, pp. 20-31, May-June 2011, doi:10.1109/MDT.2011.43
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