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Issue No.03 - May/June (2011 vol.28)
pp: 10-19
Samar Abdi , Concordia University
Yonghyun Hwang , Qualcomm
Lochi Yu , Universidad de Costa Rica
Gunar Schirner , Northeastern University
Daniel D. Gajski , University of California, Irvine
ABSTRACT
<p>Editor's note:</p><p>This article suggests a methodology to validate software applications for a multicore platform by automatically generating transaction-level models from task-level specification of the applications. Software vendors developing applications for multicore platforms can leverage this methodology for early validation.</p><p align="right"><it>&#x2014;Sandeep Shukla, Virginia Tech</it></p>
INDEX TERMS
design and test, embedded systems, multicore design, transaction-level modeling, TLM
CITATION
Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski, "Automatic TLM Generation for Early Validation of Multicore Systems", IEEE Design & Test of Computers, vol.28, no. 3, pp. 10-19, May/June 2011, doi:10.1109/MDT.2010.117
REFERENCES
1. D.D. Gajski et al., Embedded System Design: Modeling, Synthesis and Verification, Springer, 2009.
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3. C. Brandolese et al., "Source-Level Execution Time Estimation of C Programs," Proc. 9th Int'l Symp. Hardware/Software Codesign (CODES 01), ACM Press, 2001, doi:10.1145/371636.371694.
4. T. Kempf et al., "A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation," Proc. Design, Automation and Test in Europe Conf. (DATE 06), IEEE CS Press, 2006, doi:10.1109/DATE.2006.243830.
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6. Xilinx, Embedded System Tools Reference Manual, 2005.
7. T. Grötker et al., System Design with SystemC, Kluwer Academic Publishers, 2002.
8. L. Yu, S. Abdi, and D. Gajski, Transaction Level Platform Modeling in SystemC for Multi-Processor Designs, tech. report CECS-07-01, Center for Embedded Computer Systems, Univ. of California, Irvine, 2007.
9. LLVM (Low Level Virtual Machine) Project, "The LLVM Compiler Infrastructure," v. 2.8, 2010; http:/www.llvm.org.
10. Y. Hwang, S. Abdi, and D. Gajski, "Cycle-Approximate Retargetable Performance Estimation at the Transaction Level," Proc. Design, Automation and Test in Europe Conf. (DATE 08), EDAA, 2008, pp. 3-8.
11. Y. Hwang, G. Schirner, and S. Abdi, "Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support," Proc. 3rd IFIP TC 10 Int'l Embedded Systems Symposium (IESS 09), Springer, 2009, pp. 66-76.
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