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Prabhat Mishra, University of Florida
Zeljko Zilic, McGill University
Sandeep Shukla, Virginia Tech

This issue of IEEE Design and Test presents four special-theme articles that highlight challenges and recent trends of multicore architecture validation using transaction-level models. The articles cover theoretical as well as practical aspects related to high-level validation including transaction-level modeling of multicore architectures, validation, and debug of TLM models, and industrial case studies.

Index Terms:
design and test, multicore architectures, transaction-level models, transaction-level modeling, validation
Citation:
Prabhat Mishra, Zeljko Zilic, Sandeep Shukla, "Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models," IEEE Design & Test of Computers, vol. 28, no. 3, pp. 6-9, May-June 2011, doi:10.1109/MDT.2011.62
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