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IEEE Design & Test of Computers
March-April 2011 (vol. 28 no. 2)
ISSN: 0740-7475
Table of Contents
From the EIC
Domain Specific Customization
Jason Cong, University of California
Vivek Sarkar, Rice University
Glenn Reinman, University of California
Alex Bui, UCLA Medical School, Los Angeles
pp. 6-15
Power Estimation Models to Design NoC-Based MPSoCs
Low-Power Resilient Interconnections
Seung Eun Lee, Seoul Nat. Univ. of Sci. & Technol., Seoul, South Korea
Yoon Seok Yang, Texas A&M Univ., College Station, TX, USA
G S Choi, Texas A&M Univ., College Station, TX, USA
Wei Wu, Intel, Hillsboro, OR, USA
R Iyer, Intel, Hillsboro, OR, USA
pp. 30-39
Book Reviews
The Road Ahead
Roads not taken (Abstract)
Andrew B. Kahng, University of California, San Diego
pp. 74-75
Hybrid Embedded Testbench Acceleration
Chin-Lung Chuang, Dept. of Electr. Eng., Nat. Central Univ., Jungli, Taiwan
Chien-Nan Liu, Dept. of Electr. Eng., Nat. Central Univ., Jungli, Taiwan
pp. 40-51
Test Technology TC Newsletter
Screening Small-Delay Defects
M Yilmaz, Adv. Micro Devices, Sunnyvale, CA, USA
M Tehranipoor, Univ. of Connecticut, Storrs, CT, USA
pp. 52-61
CEDA Currents
Multiple-Scan-Tree Synthesis
K Shu-Min Li, Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Jr-Yang Huang, Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
pp. 62-69
The Last Byte
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