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Masood Qazi, Mahmut Sinangil, Anantha Chandrakasan, "Challenges and Directions for LowVoltage SRAM," IEEE Design & Test of Computers, vol. 28, no. 1, pp. 3243, January/February, 2011.  
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@article{ 10.1109/MDT.2010.115, author = {Masood Qazi and Mahmut Sinangil and Anantha Chandrakasan}, title = {Challenges and Directions for LowVoltage SRAM}, journal ={IEEE Design & Test of Computers}, volume = {28}, number = {1}, issn = {07407475}, year = {2011}, pages = {3243}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2010.115}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  MGZN JO  IEEE Design & Test of Computers TI  Challenges and Directions for LowVoltage SRAM IS  1 SN  07407475 SP32 EP43 EPD  3243 A1  Masood Qazi, A1  Mahmut Sinangil, A1  Anantha Chandrakasan, PY  2011 KW  design and test KW  SRAM KW  CMOS memory circuits KW  randomaccess storage KW  cache memories KW  embedded memory KW  lowpower electronics KW  lowvoltage electronics VL  28 JA  IEEE Design & Test of Computers ER   
Editor's note:
SRAMs capable of operating at extremely low supply voltages—for example, below the transistor threshold voltage—can enable ultralowpower batteryoperated systems by allowing the logic and memory to operate at the same optimal supply voltage. This review article presents SRAM techniques including new bit cells, novel sensing schemes, and read/write assist circuits for ultralowpower applications.
—Chris H. Kim, University of Minnesota
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