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Issue No.01 - January/February (2011 vol.28)
pp: 22-31
Yih Wang , Intel
Pramod Kolar , Intel
Liqiong Wei , Intel
Yong-Gee Ng , Intel
Kevin Zhang , Intel
ABSTRACT
<p>Editor's note:</p><p>Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.</p><p align="right">&#x2014;Chris H. Kim, University of Minnesota</p>
INDEX TERMS
design and test, SRAM, minimum operating voltage, VCCmin, low power, high-performance applications
CITATION
Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang, "Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design", IEEE Design & Test of Computers, vol.28, no. 1, pp. 22-31, January/February 2011, doi:10.1109/MDT.2011.5
REFERENCES
1. K. Mistry et al., "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90 nm CMOS Technology," Proc. Symp. VLSI Tech., IEEE Press, 2004, pp. 50-51.
2. K. Mistry et al., "A 45 nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," Proc. IEEE Int'l Electron Devices Meeting (IEDM 07), IEEE Press, 2007, pp. 247-250.
3. S. Natarajan et al., "A 32 nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171μm2 SRAM Cell Size in a 291 Mb Array," Proc. IEEE Int'l Electron Devices Meeting (IEDM 08), IEEE Press, 2008, doi:10.1109/IEDM.2008.4796777.
4. F. Hamzaoglu et al., "A 3.8 GHz 153 Mb SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology," IEEE J. Solid-State Circuits, vol. 44, no. 1, 2009, pp. 148-154.
5. Y. Wang et al., "A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology with Integrated Power Management," IEEE J. Solid-State Circuits, vol. 45, no. 1, 2010, pp. 103-110.
6. H. Nho et al., "A 32 nm High-k Metal Gate SRAM with Adaptive Dynamic Stability Enhancement for Low- Voltage Operation," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, 2010, pp. 346-347.
7. M. Khellah et al., "A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process with Actively Clamped Sleep Transistor," IEEE J. Solid-State Circuits, vol. 42, no. 1, 2007, pp. 233-242.
8. K. Zhang et al., "SRAM Design on 65-nm CMOS Technology with Dynamic Sleep Transistor for Leakage Reduction," IEEE J. Solid-State Circuits, vol. 40, no. 4, 2005, pp. 895-901.
9. Y. Wang et al., "A 1.1 GHz 12μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology with Integrated Leakage Reduction for Mobile Applications," IEEE J. Solid-State Circuits, vol. 43, no. 1, 2008, pp. 172-179.
10. K. Zhang et al., "A 3-GHz 70-mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," IEEE J. Solid-State Circuits, vol. 41, no. 1, 2006, pp. 146-151.
11. M. Miyazaki et al., "A 1000-MIPS/W Microprocessor Using Speed Adaptive Threshold-Voltage CMOS with Forward Bias," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 00), IEEE Press, 2000, pp. 420-421, 475.
12. M. Yamaoka and T. Kawahara, "Operating-Margin-Improved SRAM with Column-at-a-Time Body-Bias Control Technique," Proc. 33rd European Solid State Circuits Conf. (ESSCIRC 07), IEEE Press, 2007, pp. 396-399.
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