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Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design
January/February 2011 (vol. 28 no. 1)
pp. 22-31

Editor's note:

Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.

—Chris H. Kim, University of Minnesota

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Index Terms:
design and test, SRAM, minimum operating voltage, VCCmin, low power, high-performance applications
Citation:
Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang, "Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design," IEEE Design & Test of Computers, vol. 28, no. 1, pp. 22-31, Jan.-Feb. 2011, doi:10.1109/MDT.2011.5
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