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Embedded DRAM in 45-nm Technology and Beyond
January/February 2011 (vol. 28 no. 1)
pp. 14-21
Darren Anand, IBM, Essex Junction
Kevin Gorman, IBM, Essex Junction
Mark Jacunski, IBM, Essex Junction
Adrian Paparelli, IBM, Essex Junction

Editor's note:

As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.

—Leland Chang, IBM T.J. Watson Research Center

1. F. Morishita et al., "A 312-MHz 16-Mb Random-Cycle Embedded DRAM Macro with a Power-Down Data Retention Mode for Mobile Applications," IEEE J. Solid-State Circuits, vol. 40, no. 1, 2005, pp. 204-212.
2. T. Iwai et al., "Low Power Embedded DRAM Using 0.6 V Super Retention Mode with Word Line Data Mirroring," Proc. Asian Solid-State Circuits Conf. (ASSCC 09), IEEE Press, 2009, pp. 209-212.
3. M. Kaku et al., "An 833 MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications," Proc. Int'l Solid-State Circuits Conf. (ISSCC 08), IEEE Press, 2008, pp. 276-277.
4. J. Barth et al., "A 45 nm SOI Embedded DRAM Macro for POWER7 32 Mb On-Chip L3 Cache," Proc. Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, 2010, pp. 342-343.
5. S. Iyer et al., "Embedded DRAM Technology Platform for Bluegene/L Chip," IBM J. R&D, Mar.-May 2005, pp. 333-350.
6. G. Wang et al., "A 0.127 mm2 High Performance 65 nm SOI Based Embedded DRAM for On-Processor Applications," Proc. Int'l Electron Devices Meeting (IEDM 06), IEEE Press, 2006, pp. 565-568.
7. J. Dreibelbis et al., "Processor Based Built-in Self Test for Embedded DRAM," IEEE J. Solid State Circuits, vol. 33, no. 11, 1998, pp. 1731-1740.
8. K. Gorman et al., "Advancements in At-Speed Array BIST: Multiple Improvements," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, 2007, pp. 1-10.
9. K. Gorman et al., "Low Cost Test of High Bandwidth Embedded Memories," Proc. Custom Integrated Circuits Conf. (CICC 06), IEEE Press, 2006, pp. 445-448.
10. M. Ouellette et al, "An On-Chip Self-Repair Calculation and Fusing Methodology," IEEE Design & Test, vol. 20, no. 5, 2003, pp. 67-75.

Index Terms:
design and test; semiconductor memories; DRAM; design styles; cache memories; reliability, testing, and fault tolerance; diagnostics; error checking; redundant design; test generation
Darren Anand, Kevin Gorman, Mark Jacunski, Adrian Paparelli, "Embedded DRAM in 45-nm Technology and Beyond," IEEE Design & Test of Computers, vol. 28, no. 1, pp. 14-21, Jan.-Feb. 2011, doi:10.1109/MDT.2011.2
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