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| Darren Anand, Kevin Gorman, Mark Jacunski, Adrian Paparelli, "Embedded DRAM in 45-nm Technology and Beyond," IEEE Design & Test of Computers, vol. 28, no. 1, pp. 14-21, January/February, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2011.2, author = {Darren Anand and Kevin Gorman and Mark Jacunski and Adrian Paparelli}, title = {Embedded DRAM in 45-nm Technology and Beyond}, journal ={IEEE Design & Test of Computers}, volume = {28}, number = {1}, issn = {0740-7475}, year = {2011}, pages = {14-21}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2011.2}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Embedded DRAM in 45-nm Technology and Beyond IS - 1 SN - 0740-7475 SP14 EP21 EPD - 14-21 A1 - Darren Anand, A1 - Kevin Gorman, A1 - Mark Jacunski, A1 - Adrian Paparelli, PY - 2011 KW - design and test; semiconductor memories; DRAM; design styles; cache memories; reliability KW - testing KW - and fault tolerance; diagnostics; error checking; redundant design; test generation VL - 28 JA - IEEE Design & Test of Computers ER - | |||
Editor's note:
As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.
—Leland Chang, IBM T.J. Watson Research Center
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