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Issue No.01 - January/February (2011 vol.28)
pp: 14-21
Darren Anand , IBM, Essex Junction
Kevin Gorman , IBM, Essex Junction
Mark Jacunski , IBM, Essex Junction
Adrian Paparelli , IBM, Essex Junction
ABSTRACT
<p>Editor's note:</p><p>As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.</p><p align="right">&#x2014;Leland Chang, IBM T.J. Watson Research Center</p>
INDEX TERMS
design and test; semiconductor memories; DRAM; design styles; cache memories; reliability, testing, and fault tolerance; diagnostics; error checking; redundant design; test generation
CITATION
Darren Anand, Kevin Gorman, Mark Jacunski, Adrian Paparelli, "Embedded DRAM in 45-nm Technology and Beyond", IEEE Design & Test of Computers, vol.28, no. 1, pp. 14-21, January/February 2011, doi:10.1109/MDT.2011.2
REFERENCES
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8. K. Gorman et al., "Advancements in At-Speed Array BIST: Multiple Improvements," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, 2007, pp. 1-10.
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