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| Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou, "A Built-in Method to Repair SoC RAMs in Parallel," IEEE Design & Test of Computers, vol. 27, no. 6, pp. 46-57, November/December, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2010.121, author = {Tsu-Wei Tseng and Jin-Fu Li and Chih-Sheng Hou}, title = {A Built-in Method to Repair SoC RAMs in Parallel}, journal ={IEEE Design & Test of Computers}, volume = {27}, number = {6}, issn = {0740-7475}, year = {2010}, pages = {46-57}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2010.121}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - A Built-in Method to Repair SoC RAMs in Parallel IS - 6 SN - 0740-7475 SP46 EP57 EPD - 46-57 A1 - Tsu-Wei Tseng, A1 - Jin-Fu Li, A1 - Chih-Sheng Hou, PY - 2010 KW - design and test KW - SoC KW - embedded memories KW - built-in self-repair KW - redundancy analysis KW - yield improvement VL - 27 JA - IEEE Design & Test of Computers ER - | |||
Built-in-self-repair is an enabling approach for improving memory yield in system-on-chip designs. Reducing the overhead of repair circuits while minimizing the test and repair time is of prime importance. This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework.
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