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A Built-in Method to Repair SoC RAMs in Parallel
November/December 2010 (vol. 27 no. 6)
pp. 46-57
Tsu-Wei Tseng, National Central University
Jin-Fu Li, National Central University
Chih-Sheng Hou, National Central University

Editor's note:

Built-in-self-repair is an enabling approach for improving memory yield in system-on-chip designs. Reducing the overhead of repair circuits while minimizing the test and repair time is of prime importance. This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework.

Swarup Bhunia, Case Western Reserve University

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Index Terms:
design and test, SoC, embedded memories, built-in self-repair, redundancy analysis, yield improvement
Citation:
Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou, "A Built-in Method to Repair SoC RAMs in Parallel," IEEE Design & Test of Computers, vol. 27, no. 6, pp. 46-57, Nov.-Dec. 2010, doi:10.1109/MDT.2010.121
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