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The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane
November/December 2010 (vol. 27 no. 6)
pp. 36-45
Rajiv Joshi, IBM Corporation,
Rouwaida Kanj, IBM, round Rock
Anthony Pelella, IBM Corporation,
Arthur tuminaro, IBM Corporation,
Yuen Chan, IBM Corporation,

Editor's note:

Statistical approaches for yield estimation and robust design are vital in the current variation-dominated design era. This article presents a mixture importance sampling methodology to enable yield-driven design and extends its application beyond memories to peripheral circuits and logic blocks.

—Rahul Rao, IBM

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Index Terms:
design and test, DFM, memory, logic, yield, test, variation-tolerant designs
Rajiv Joshi, Rouwaida Kanj, Anthony Pelella, Arthur tuminaro, Yuen Chan, "The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane," IEEE Design & Test of Computers, vol. 27, no. 6, pp. 36-45, Nov.-Dec. 2010, doi:10.1109/MDT.2010.95
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