This Article 
 Bibliographic References 
 Add to: 
Postsilicon Adaptation for Low-Power SRAM under Process Variation
November/December 2010 (vol. 27 no. 6)
pp. 26-35
Minki Cho, Georgia Institute of Technology
Jason Schlessman, Princeton University
Hamid Mahmoodi, San Francisco State University
Marilyn Wolf, Georgia Institute of Technology
Saibal Mukhopadhyay, Georgia Institute of Technology

Editor's note:

Due to the high density requirement for embedded memories, such memories are highly vulnerable to process variation–induced failures. A conservative design approach can largely affect memory density and access performance. This article analyzes variation effects in SRAM and presents low-cost, adaptive postsilicon repair mechanisms.

—Swarup Bhunia, Case Western Reserve University

1. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS," IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, vol. 24, no. 12, 2005, pp. 1859-1880.
2. S. Mukhopadhyay et al., "Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS," IEEE J. Solid State Circuits, vol. 42, no. 6, 2007, pp. 1370-1382.
3. K. Zhang et al., "A 3-GHz 70MB SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 05), vol. 1, IEEE Press, 2005, pp. 474-475, 611.
4. S. Ohbayashi et al., "A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits," Proc. Symp. VLSI Circuits, IEEE Press, 2006, pp. 17-18.
5. A.K. Djahromi et al., "Cross Layer Error Exploitation for Aggressive Voltage Scaling," Proc. 8th IEEE Int'l Symp. Quality Electronic Design (ISQED 07), IEEE CS Press, 2007, pp. 192-197.
6. K. Yi et al., "A Partial Memory Protection Scheme for Higher Effective Yield of Embedded Memory for Video Data," Proc. 13th Asia-Pacific Computer Systems Architecture Conf. (ACSAC 08), IEEE CS Press, 2008, pp. 273-278.
7. M. Cho et al., "Reconfigurable SRAM Architecture with Spatial Voltage Scaling for Low Power Mobile Multimedia Applications," to be published in IEEE Trans. Very Large Scale Integration (VLSI) Systems.
8. S. Mukhopadhyay et al., "Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure," Proc. IEEE Int'l Solid State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 400-401, 611.
9. M. Yamaoka et al., "65 nm Low-Power High-Density SRAM Operable at 1.0 V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS," IEEE Int'l Solid State Circuits Conf. (ISSCC 08), IEEE Press, 2008, pp. 383-385, 622.
10. N.N. Mojumder et al., "Self-Repairing SRAM Using On-Chip Detection and Compensation," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 18, no. 1, 2010, pp. 75-84.
11. Z. Wang et al., "Image Quality Assessment: From Error Visibility to Structural Similarity," IEEE Trans. Image Processing, vol. 13, no. 4, 2004, pp. 600-612.
12. J. Schlessman et al., "Hardware/Software Co-design of an FPGA-Based Embedded Tracking System," Proc. IEEE Conf. Computer Vision and Pattern Recognition (CVPRW 06), IEEE Press, 2006, pp. 123-133.

Index Terms:
design and test, low-power, multimedia, SRAM, reconfiguration, process variations, image processing, postsilicon adaptation
Minki Cho, Jason Schlessman, Hamid Mahmoodi, Marilyn Wolf, Saibal Mukhopadhyay, "Postsilicon Adaptation for Low-Power SRAM under Process Variation," IEEE Design & Test of Computers, vol. 27, no. 6, pp. 26-35, Nov.-Dec. 2010, doi:10.1109/MDT.2010.137
Usage of this product signifies your acceptance of the Terms of Use.