The Community for Technology Leaders
RSS Icon
Issue No.05 - September/October (2010 vol.27)
pp: 26-35
Ewerson Luiz de Souza Carvalho , Pontifícia Universidade Católica do Rio Grande do Sul
Ney Laert Vilar Calazans , Pontifícia Universidade Católica do Rio Grande do Sul
Fernando Gehm Moraes , Pontifícia Universidade Católica do Rio Grande do Sul
<p>Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.</p>
design and test, dynamic task mapping, MPSoC, SoC, NoC
Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes, "Dynamic Task Mapping for MPSoCs", IEEE Design & Test of Computers, vol.27, no. 5, pp. 26-35, September/October 2010, doi:10.1109/MDT.2010.106
1. T. Lei and S. Kumar, "A Two-Step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture," Proc. Euromicro Symp. Digital System Design (DSD 03), IEEE Press, 2003, pp. 180-187.
2. D. Wu, B. Al-Hashimi, and P. Eles, "Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems," Proc. Design, Automation and Test in Europe (DATE 03), IEEE CS Press, 2003, pp. 90-95.
3. S. Murali and G. De Micheli, "Bandwidth-Constrained Mapping of Cores onto NoC Architectures," Proc. Design, Automation and Test in Europe (DATE 04), IEEE CS Press, 2004, pp. 896-901.
4. S. Manolache, P. Eles, and Z. Peng, "Fault and Energy-Aware Communication Mapping with Guaranteed Latency for Applications Implemented on NoC," Proc. 42nd Annual Design Automation Conf. (DAC 05), ACM Press, 2005, pp. 266-269.
5. J. Hu and R. Marculescu, "Energy- and Performance-Aware Mapping for Regular NoC Architectures," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, 2005, pp. 551-562.
6. C. Marcon et al., "Comparison of NoC Mapping Algorithms Targeting Low Energy Consumption," IET Computers & Digital Techniques, vol. 2, no. 6, 2008, pp. 471-482.
7. A. Ngouanga et al., "A Contextual Resources Use: A Proof of Concept through the APACHES Platform," Proc. Design and Diagnostics of Electronic Circuits and Systems (DDECS 06), IEEE Press, 2006, pp. 42-47.
8. L. Smit, J. Hurink, and G. Smit, "Run-Time Mapping of Applications to a Heterogeneous SoC," Proc. Int'l Symp. System-on-Chip (SoC 05), IEEE Press, 2005, pp. 78-81.
9. A. Mehran, A. Khademzadeh, and S. Saeidi, "DSM: A Heuristic Dynamic Spiral Mapping Algorithm for Network on Chip," IEICE Electronics Express, vol. 5, no. 13, 2008, pp. 464-471.
10. C.-L. Chou, U. Ogras, and R. Marculescu, "Energy- and Performance-Aware Incremental Mapping for Networks on Chip with Multiple Voltage Levels," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 10, 2008, pp. 1866-1879.
11. M. Al Faruque, R. Krist, and J. Henkel, "ADAM: Run-Time Agent-Based Distributed Application Mapping for On-Chip Communication," Proc. 45th Annual Design Automation Conf. (DAC 08), ACM Press, 2008, pp. 760-765.
12. E. Carvalho and F. Moraes, "Congestion-Aware Task Mapping in Heterogeneous MPSoCs," Proc. Int'l Symp. System-on-Chip (SoC 08), IEEE Press, 2008, pp. 1-4.
703 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool