This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Speeding Up Physical Synthesis with Transactional Timing Analysis
September/October 2010 (vol. 27 no. 5)
pp. 14-25
ASCII Text
x 
 
David Papa, Michael D. Moffitt, Charles J. Alpert, Igor L. Markov, "Speeding Up Physical Synthesis with Transactional Timing Analysis," IEEE Design & Test of Computers, vol. 27, no. 5, pp. 14-25, September/October, 2010.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2010.76,
author = {David Papa and Michael D. Moffitt and Charles J. Alpert and Igor L. Markov},
title = {Speeding Up Physical Synthesis with Transactional Timing Analysis},
journal ={IEEE Design & Test of Computers},
volume = {27},
number = {5},
issn = {0740-7475},
year = {2010},
pages = {14-25},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2010.76},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Speeding Up Physical Synthesis with Transactional Timing Analysis
IS - 5
SN - 0740-7475
SP14
EP25
EPD - 14-25
A1 - David Papa,
A1 - Michael D. Moffitt,
A1 - Charles J. Alpert,
A1 - Igor L. Markov,
PY - 2010
KW - design and test
KW - algorithms
KW - static timing analysis
KW - timing-driven placement
KW - physical synthesis
KW - transactional timing analysis
VL - 27
JA - IEEE Design & Test of Computers
ER -
 
David Papa, University of Michigan, Ann Arbor, and IBM Austin
Michael D. Moffitt, IBM Austin Research Lab
Charles J. Alpert, IBM Austin Research Lab
Igor L. Markov, University of Michigan , Ann Arbor

Modern physical-synthesis flows operate on very large designs and perform increasingly aggressive timing optimizations. Traditional incremental timing analysis now represents the single greatest bottleneck in such optimizations and lacks the features necessary to support them efficiently. This article describes a paradigm of transactional timing analysis, which, together with incremental updates, offers an efficient, nested undo functionality that avoids significant timing calculations.

1. L. Trevillyan et al., "An Integrated Environment for Technology Closure of Deep-Submicron IC Designs," IEEE Design & Test, vol. 21, no. 1, 2004, pp. 14-22.
2. M.D. Moffitt et al., "Path Smoothing via Discrete Optimization," Proc. 45th Design Automation Conf. (DAC 08), ACM Press, 2008, pp. 724-727.
3. L.N. Kannan, P.R. Suaris, and H.-G. Fang, "A Methodology and Algorithms for Post-Placement Delay Optimization," Proc. 31st Design Automation Conf. (DAC 94), ACM Press, 1994, pp. 327-332.
4. D.A. Papa et al., "Rumble: An Incremental, Timing-Driven, Physical-Synthesis Optimization Algorithm," Proc. Int'l Symp. Physical Design (ISPD 08), ACM Press, 2008, pp. 2-9.
5. H. Ren et al., "Hippocrates: First-Do-No-Harm Detailed Placement," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC 07), IEEE CS Press, 2007, pp. 141-146.
6. K.-H. Chang, I.L. Markov, and V. Bertacco, "Safe Delay Optimization for Physical Synthesis," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC 07), IEEE CS Press, 2007, pp. 628-633.
7. A.D. Drumm, R.C. Itskin, and K.W. Todd, Method and Apparatus for Performing Timing Correction Transformations on a Technology-Independent Logic Model during Logic Synthesis, US patent 5,003,487, to IBM Corp., Patent and Trademark Office, 1991.
8. R.P. Abato et al., Incremental Timing Analysis, US patent 5,508,937, to IBM Corp., Patent and Trademark Office, 1996.
9. J. Lee and D.T. Tang, "An Algorithm for Incremental Timing Analysis," Proc. 32nd Design Automation Conf. (DAC 95), ACM Press, 1995, pp. 696-701.
10. S.S. Sapatnekar, "Efficient Calculation of All-Pairs Input-to-Output Delays in Synchronous Sequential Circuits," Proc. Int'l Symp. Circuits and Systems (ISCAS 96), IEEE Press, 1996, pp. 724-727.
11. A. Mondal and C.A. Mandal, "A New Approach to Timing Analysis Using Event Propagation and Temporal Logic," Proc. Design, Automation and Test in Europe Conf., (DATE 04), IEEE CS Press, 2004, pp. 1198-1203.
12. D. Das et al., "FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling," Proc. Int'l Conf. Computer Design (ICCD 06), IEEE Press, 2006, pp. 43-49.
13. M.A. Kazda et al., System and Method for Sign-Off Timing Closure of a VLSI Chip, US patent 7581201, to IBM Corp., Patent and Trademark Office, 2009.
14. D. Bronnenberg, "Static Timing Analysis Increases ASIC Performance," Integrated System Design, June 1999.
15. L. Scheffer, L. Lavagno, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology CRC Press, 2006.
16. W.E. Donath et al., "Transformational Placement and Synthesis," Proc. Design, Automation and Test in Europe Conf. (DATE 00), IEEE CS Press, 2000, pp. 194-201.
17. J. Vygen, "Slack in Static Timing Analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, 2006, pp. 1876-1885.
18. W.E. Donath and D.J. Hathaway, Distributed Static Timing Analysis, US patent 6,557,151, to IBM Corp., Patent and Trademark Office, 2003.

Index Terms:
design and test, algorithms, static timing analysis, timing-driven placement, physical synthesis, transactional timing analysis
Citation:
David Papa, Michael D. Moffitt, Charles J. Alpert, Igor L. Markov, "Speeding Up Physical Synthesis with Transactional Timing Analysis," IEEE Design & Test of Computers, vol. 27, no. 5, pp. 14-25, Sept.-Oct. 2010, doi:10.1109/MDT.2010.76
Usage of this product signifies your acceptance of the Terms of Use.