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Measurement-Based Ring Oscillator Variation Analysis
September/October 2010 (vol. 27 no. 5)
pp. 6-13
Koh Johguchi, Hiroshima University
Akihiro Kaya, Hiroshima University
Shinya Izumi, Renesas Technology
Hans Mattausch, Hiroshima University
Tetsushi Koide, Hiroshima University
Norio Sadachika, Tsuneishi Shipbuilding

As transistor size scales down, unavoidable process variations are rapidly increasing. Consequently, it's essential for designers to accurately estimate within-die and interdie variations so that circuits and integrated systems can operate correctly. This article describes an analysis of ring oscillators that were designed in 180-nm and 100-nm CMOS technologies, and discusses the oscillators' frequency variations as determined for different stage numbers and supply voltages.

1. K.J. Kuhn, "Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS," Proc. Int'l Electron Devices Meeting (IEDM 07), IEEE Press, 2007, pp. 471-474.
2. A. Srivastava et al., "Modeling and Analysis of Leakage Power Considering Within-Die Process Variations," Proc. Int'l Symp. Low Power Electronics and Design, ACM Press, 2002, pp. 64-67.
3. BSIM4 Compact Model Summary (online); bsim4.html.
4. H.J. Mattausch et al., "Correlating Microscopic and Macroscopic Variation with Surface-Potential Compact Model," IEEE Electron Device Letters, vol. 30, no. 8, 2009, pp. 873-875.
5. M. Miura-Mattausch, H.J. Mattausch, and T. Ezaki, The Physics and Modeling of MOSFETs: Surface-Potential Model HiSIM, World Scientific, 2008.
6. M. Miura-Mattausch et al., "HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation," IEEE Trans. Electron Devices, vol. 53, no. 9, 2006, pp. 1994-2007.
7. J. Bastos et al., "Influence of Die Attachment on MOS Transistor Matching," Proc. Int'l Conf. Microelectronic Test Structures (ICMTS 96), IEEE Press, 1996, pp. 27-31.
8. M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, "Matching Properties of MOS Transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, 1989, pp. 1433-1439.
9. G. Gildenblat et al., "PSP: An Advanced Surface- Potential-Based MOSFET Model for Circuit Simulation," IEEE Trans. Electron Devices, vol. 53, no. 9, 2006, pp. 1979-1993.
10. H.C. Pao and C.T. Sah, "Effects of Diffusion Current on Characteristics of Metal-Oxide (Insulator)–Semiconductor Transistor (MOST)," Solid State Electronics, vol. 9, no. 10, 1966, pp. 927-937.
11. A. Kaya et al., "Analysis of Process Variations in 90-nm CMOS Technology Using Ring Oscillators," Proc. 15th Workshop Synthesis and System Integration of Mixed Information Technologies (SASIMI 09), SASIMI Workshop, 2009, pp. 446-449.
12. K. Johguchi et al., "Within-Die/Wafer Variation Analysis of Basic CMOS Circuits Based on Surface-Potential-Model HiSIM2," Proc. Int'l Conf. Solid State Devices and Materials, Japan Soc. of Applied Physics, (SSDM 09), 2009, pp. 1072-1073.

Index Terms:
design and test, within-wafer variation, within-die variation, CMOS, ring oscillators, compact model, surface potential, low power
Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Mattausch, Tetsushi Koide, Norio Sadachika, "Measurement-Based Ring Oscillator Variation Analysis," IEEE Design & Test of Computers, vol. 27, no. 5, pp. 6-13, Sept.-Oct. 2010, doi:10.1109/MDT.2010.57
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