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Measurement-Based Ring Oscillator Variation Analysis
September/October 2010 (vol. 27 no. 5)
pp. 6-13
Koh Johguchi, Hiroshima University
Akihiro Kaya, Hiroshima University
Shinya Izumi, Renesas Technology
Hans Mattausch, Hiroshima University
Tetsushi Koide, Hiroshima University
Norio Sadachika, Tsuneishi Shipbuilding

As transistor size scales down, unavoidable process variations are rapidly increasing. Consequently, it's essential for designers to accurately estimate within-die and interdie variations so that circuits and integrated systems can operate correctly. This article describes an analysis of ring oscillators that were designed in 180-nm and 100-nm CMOS technologies, and discusses the oscillators' frequency variations as determined for different stage numbers and supply voltages.

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Index Terms:
design and test, within-wafer variation, within-die variation, CMOS, ring oscillators, compact model, surface potential, low power
Citation:
Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Mattausch, Tetsushi Koide, Norio Sadachika, "Measurement-Based Ring Oscillator Variation Analysis," IEEE Design & Test of Computers, vol. 27, no. 5, pp. 6-13, Sept.-Oct. 2010, doi:10.1109/MDT.2010.57
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