Issue No.04 - July/August (2010 vol.27)
Published by the IEEE Computer Society
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2010.91
<p>This month's Test Technology TC Newsletter features highlights of past events—28th IEEE VLSI Test Symposium and 19th IEEE North Atlantic Test Workshop—and upcoming events: 16th IEEE International On-Line Testing Symposium, 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, and 40th International Test Conference.</p>
Past TTTC Events
28th IEEE VLSI Test Symposium (VTS 2010)
19–22 April 2010
Santa Cruz, California
The 2010 IEEE VLSI Test Symposium program included articles in various areas such as emerging trends and novel concepts in test, verification, fault and defect tolerance, and validation of microelectronic circuits and systems, analog and RF circuits, digital circuits, memory test, and reliability. In addition to the papers presented at VTS'10, the innovative-practices track and special sessions were popular among researchers from both academia and industry. The keynote speech was given by Robert Madge, director of technology at LSI, and the invited keynote was given by Ron Collett, CEO and president, Nemetrics. Similar to last year's symposium, a student poster presentation and a best-doctoral- thesis contest were included in this year's program as well.
19th IEEE North Atlantic Test Workshop (NATW 2010)
12–14 May 2010
Hopewell Junction, New York
The IEEE North Atlantic Test Workshop provides a forum for discussions on the latest issues relating to high-quality, economical, and efficient testing methodologies and designs. With the increasing complexity in both design and test of integrated circuits and systems, the 19th NATW featured the theme: "Economics: The Dirtiest Word in Test" and a panel dedicated to intellectual property. This year, NATW included 21 papers from industry and academia, including 10 student papers competing for the Jake Karrfalt Best Student Paper Award. In addition, the workshop included a keynote address by Leon Stok of IBM titled "Complexity in High-end Processor Design," a Thursday invited address by John Hayes on "Soft Errors," and a Friday invited address by Dave Lackey of IBM on "A Design Automation Tool Flow for DFT." The 2010 workshop was held at Le Chambord in Hopewell Junction, New York, and was sponsored, in part, by the Green Mountain Section of IEEE. NATW corporate and academic supporters for 2010 included Cadence, Mentor Graphics, SynTest Technologies, Auburn University Wireless Engineering Research and Education Center, and the Vermont Chapter of the IEEE Solid State Circuits Society.
Upcoming TTTC Events
16th IEEE International On-Line Testing Symposium (IOLTS 2010)
5–7 July 2010
Corfu Island, Greece
Issues related to on-line testing are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as to pressure for low-cost products. There is a corresponding, increasing demand for cost-effective on-line testing techniques. These needs have increased dramatically with the introduction of very deep submicron and nanometer technologies that adversely impact noise margins, process, voltage and temperature variations, aging, and wearout, and make integrating on-line testing and fault tolerance mandatory in many modern ICs. The International On-Line Testing Symposium (IOLTS) is an established forum for presenting novel ideas and experimental data in these areas. The symposium also emphasizes on-line testing in the continuous operation of large applications such as wired, cellular, and satellite telecommunication, as well as in secure chips. The symposium is sponsored by the IEEE Computer Society Test Technology Technical Council and organized by TIMA Laboratory, the University of Athens, and the University of Piraeus.
25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2010)
6–8 October 2010
DFT is an annual symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems, including emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing—and affected by faults during system operation—are of interest.
40th International Test Conference (ITC 2010)
31 October–5 November 2010
The International Test Conference, billed as "the cornerstone of Test Week events," is the world's premier conference dedicated to the electronic test of devices, boards, and systems. ITC covers the complete test cycle from design verification, test, diagnosis, failure analysis, and back to process and design improvement. At ITC, test and design professionals can face the challenges confronting the industry, and discover how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. Test Week activities take place 31 Oct.–5 Nov. The conference will focus on adaptive test, built-in self-test, low-cost ATE, RF test, test data analysis, and many more topics.
Newsletter Editor's Invitation
I would appreciate input and suggestions about the newsletter from the test community. Please forward your ideas, contributions, and information on awards, conferences, and workshops to Mohammad Tehranipoor, Electrical and Computer Engineering Department, Univ. of Connecticut, 371 Fairfield Way, Storrs, CT 06269-2157; email@example.com.
Editor, TTTC Newsletter