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Published by the IEEE Computer Society
Chips in 3D
This is a review of Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures (by Yuan Xie, Jason Cong, and Sachin Sapatnekar, eds.).
The promise of highly profitable 3D technologies has energized the electronics industry, where 3D integration of semiconductor chips may breathe new life into Moore's law. However, delivering on promises and avoiding pitfalls is often harder than anyone thinks. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures documents early efforts by key researchers in 3D VLSI, computer architecture, and EDA. It also offers several perspectives on the future of 3D integration.
In December 2009, moviegoers worldwide were stunned with lifelike 3D images in James Cameron's Avatar. While critics predicted a box office fiasco, box office analysts estimated a huge success—"the holy grail of 3D has finally arrived," proclaimed one of them. In just 19 days, Avatar grossed $1 billion worldwide, and two months later it won three Academy Awards. The film's $237 million budget provided an impressive ROI.
In a related vein, the promise of highly profitable 3D technologies has similarly energized the electronics industry, where 3D integration of semiconductor chips may breathe new life into Moore's law. However, delivering on promises and avoiding pitfalls is often harder than we think. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures documents early efforts by key researchers in 3D VLSI, computer architecture, and EDA. It also offers several perspectives on the future of 3D integration.
In the first two chapters, IBM researchers discuss semiconductor scaling, the promise of 3D stacking, and relevant process technology issues. Interfaces between individual chips in a 3D stack are implemented by through-silicon vias (TSVs), whose cost, size, parasitics, and reliability are life-and-death issues for 3D products. First applications of 3D stacking are likely to position memory chips on top of random-logic chips. This is particularly useful in CPU design, as explained in Chapter 7, which outlines how CPU caches may be organized in 3D and how diagnostic modules can be embedded in 3D designs with little overhead, to make CPUs self-aware through thermal sensing. Chapter 9 offers a detailed design example, in which DRAM is stacked atop a CPU core, with short low-latency links, allowing a designer to eliminate CPU caches.
Chapters 3 through 6 focus on thermal issues in 3D system design and EDA tools. To put it simply, stacking operational chips in 3D does not bode well for heat transfer and requires additional effort to balance heat distribution. Chapter 3 treats this phenomenon in more detail through recently developed analysis techniques, and also discusses power delivery challenges for 3D ICs. Chapters 4 and 5 cover thermally aware floorplanning and placement. The learning curve can be steep here if you're not up to date with recent literature on conventional floorplanning and placement. Chapter 6 advocates, first, inserting thermal TSVs whose main purpose is to conduct heat better than silicon does, and second, making routing thermally aware to provide vias so they can improve the thermal profile. Chapter 8 presents a design of a network-on-chip (NoC) architecture with 3D integration, complete with 3D buses and routers.
Chapter 10 offers system-level cost analysis for 3D chips and several ideas for cost optimization. It points out that the reduction of interconnect length due to 3D integration may allow for a smaller number of wiring layers. Chapter 10 also explains how to reuse masks by making all active layers identical.
Three-Dimensional Integrated Circuit Design is structured clearly, includes a global index of terms, and features reference lists in every chapter. It covers a number of important topics in 3D ICs, but does not say much about clock network design and circuit test. Testing TSVs will be important when TSVs become thinner. Furthermore, cost-effective manufacturing requires that different 2D chips be tested before they are stacked, otherwise a single bad chip would fail the entire 3D assembly and waste good 2D chips (see, e.g., "Test Challenges for 3D Integrated Circuits," H.-H.S. Lee and K. Chakrabarty, IEEE Design & Test, vol. 26, no. 5, 2009, pp. 26-35). Such circuit-test considerations affect both 3D chip design and design automation. For example, partitioning minimal testable units and clock domains across multiple active layers would complicate separate testing of 2D chips. A CPU architect might be able to carefully arrange functional units on different layers, and yet make them testable. However, ASIC and SoC partitioning is less straightforward, and automatic 3D place-and-route techniques discussed in the book do not account for scan chains or clock domains. These complications, along with the fairly large size of TSVs in current and near-future technologies, may limit practical 3D physical design to the assembly of independently testable 2D blocks.
With the omission of testing and clocking, the authors provide comprehensive coverage of key issues in 3D VLSI and IC design. However, as in any emerging field, new research will continue to appear in conferences and journals at a rapid pace. Further studies will likely uncover additional complications and limitations of 3D stacking, while porting state-of-the-art 2D EDA techniques to 3D, subject to these limitations, will remain challenging. For example, Mark Bohr, an Intel Senior Fellow, was recently quoted as saying "It does not make sense for Intel to go to 3D with CPU cache memory…due to interface speed issues." A VLSI Research report, according to EE Times, has observed that "Only CMOS image sensors are using TSV in production today" and that memories with TSVs have been [at the] "altar for three years. [The] bride has not arrived."
What should we expect from 3D integration in terms of commercial success? What is required to facilitate 3D design? In the absence of a crystal ball, we can try drawing parallels and looking for similarities.
To briefly revisit the Avatar anecdote: James Cameron wrote a script for the movie in 1994, but concluded that the necessary optical and software technologies were not yet available to achieve his vision. In 2005, 20th Century Fox gave him $10 million to produce a prototype. After finishing the screenplay, Cameron developed his own Reality Camera System to film in 3D. The system combined two high-definition cameras in a single camera body to improve visual resolution and depth perception.
The filming finally started in 2007 and required innovations in special-effects software, to better align traditional real-life shots with computer-generated graphics. The lead visual-effects company at one point employed 900 people to work at a 35,000-processor rendering farm with 1 petabyte of storage (this system ranked 195th in the list of the world's most powerful supercomputers). When Avatar opened to great success, the media reported that some fans "have experienced withdrawal symptoms after seeing the film because they longed to enjoy the beauty of the alien world Pandora."
If the wild success of 3D cinematography is any indication, customers of the first 3D chips will also be firmly hooked on the new technology. Consequently, the designers of 3D chips, as well as 3D integration researchers and students, will need to understand the technologies described in the book by Xie, Cong, and Sapatnekar.