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| Pouria Bastani, Nick Callegari, Li-C Wang, Magdy S. Abadir, "Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch," IEEE Design & Test of Computers, vol. 27, no. 3, pp. 42-53, May/June, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2009.95, author = {Pouria Bastani and Nick Callegari and Li-C Wang and Magdy S. Abadir}, title = {Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch}, journal ={IEEE Design & Test of Computers}, volume = {27}, number = {3}, issn = {0740-7475}, year = {2010}, pages = {42-53}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.95}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch IS - 3 SN - 0740-7475 SP42 EP53 EPD - 42-53 A1 - Pouria Bastani, A1 - Nick Callegari, A1 - Li-C Wang, A1 - Magdy S. Abadir, PY - 2010 KW - design and test KW - statistical learning KW - timing mismatch KW - statistical diagnosis VL - 27 JA - IEEE Design & Test of Computers ER - | |||
For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how features can be interpreted properly.
1. C. Bittlestone et al., "Architecting ASIC Libraries and Flows in Nanometer Era," Proc. 40th Design Automation Conf., (DAC 03), ACM Press, 2003, pp. 776-781.
2. P. Bastani et al., "Analyzing the Risk of Timing Modeling Based on Path Delay Tests," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, 2007, pp. 251-260.
3. T. Thiel, "Have I Really Met Timing?—Validating PrimeTime Timing Reports with Spice," Proc. Design, Automation and Test in Europe Conf. (DATE 04), IEEE CS Press, 2004, pp. 114-119.
4. D. Josephson, "The Manic Depression of Microprocessor Debug," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 657-663.
5. P. Zuchowski et al., "Process and Environmental Variation Impacts on ASIC Timing," Proc. Int'l Conf. Computer-Aided Design (ICCAD 04), IEEE CS Press, 2004, pp. 336-342.
6. C. Pryon et al., "Silicon Symptoms to Solutions: Applying Design-for-Debug Techniques," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 664-672.
7. S.R. Nassif, "Modeling and Forecasting of Manufacturing Variations," Proc. Int'l Workshop Statistical Metrology, IEEE Press, 2000, pp. 2-10.
8. S. Pant and E. Chiprout, "Power Grid Physics and Implications for CAD," Proc. 43rd Design Automation Conf. (DAC 06), ACM Press, 2006, pp. 199-204.
9. P. Larsson and C. Svensson, "Noise in Digital Dynamic CMOS Circuits," IEEE J. Solid-State Circuits, vol. 29, no. 6, 1994, pp. 655-663.
10. P. Bastani et al., "Speedpath Prediction Based on Learning from a Small Set of Examples," Proc. 45th Design Automation Conf. (DAC 08), ACM Press, 2008, pp. 217-222.
11. J. Shawe-Taylor and N. Cristianini, Kernel Methods for Pattern Analysis, Cambridge Univ. Press, 2004.
12. P. Bastani et al., "Statistical Diagnosis of Unmodeled Timing Effect," Proc. 45th Design Automation Conf. (DAC 08), ACM Press, 2008, pp. 355-360.