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Issue No.03 - May/June (2010 vol.27)
pp: 42-53
Pouria Bastani , University of California Santa Barbara, Santa Barbara
Nick Callegari , University of California Santa Barbara, Santa Barbara
Li-C Wang , University of California, Santa Barbara , Santa Barbara
Magdy S. Abadir , Freescale, Austin
<p>For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how features can be interpreted properly.</p>
design and test, statistical learning, timing mismatch, statistical diagnosis
Pouria Bastani, Nick Callegari, Li-C Wang, Magdy S. Abadir, "Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch", IEEE Design & Test of Computers, vol.27, no. 3, pp. 42-53, May/June 2010, doi:10.1109/MDT.2009.95
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