This Article 
 Bibliographic References 
 Add to: 
Economic Analysis of the HOY Wireless Test Methodology
May/June 2010 (vol. 27 no. 3)
pp. 20-30
YuTsao Hsing, National Tsing Hua University, Hsinchu
LiMing Denq, National Tsing Hua University, Hsinchu
Chao-Hsun Chen, National Tsing Hua University, Hsinchu
Cheng-Wen Wu, National Tsing Hua University, Hsinchu

The HOY (Hypothesis, Odyssey, and Yield) test system provides wireless test access and embedded DFT, while offering lower cost and better performance than conventional ATE. This article briefly describes HOY, then proposes a test cost model to compare it with conventional ATE, and analyzes the test cost of these two methods for different manufacturing processes, area overheads, die sizes, manufacturing volumes, and test times.

1. J. Gatej et al., "Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 1040-1049.
2. R. Rajsuman, N. Masuda, and K. Yamashita, "Architecture and Design of an Open ATE to Incubate the Development of Third-Party Instruments," IEEE Trans. Instrumentation and Measurement, vol. 54, no. 5, 2005, pp. 1678-1698.
3. H. Eberle, A. Wander, and N. Gura, "Testing Systems Wirelessly," Proc. 22nd IEEE VLSI Test Symp. (VTS 04), IEEE CS Press, 2004, pp. 335-340.
4. M.F. Chang et al., "RF/Wireless Interconnect for Inter- and Intra-chip Communications," Proc. IEEE, vol. 89, no. 4, 2001, pp. 456-466.
5. C.-W. Wu et al., "The HOY Tester—Can IC Testing Go Wireless?" Proc. Int'l Symp. VLSI Design, Automation and Test (VLSI-DAT 06), IEEE Press, 2006, pp. 183-186.
6. T.-W. Ko et al., "Stable Performance MAC Protocol for HOY Wireless Tester under Large Population," Proc. Int'l Symp. VLSI Design, Automation and Test (VLSI-DAT 07), IEEE Press, 2007, pp. 160-163.
7. J.-J. Liou et al., "A Prototype of a Wireless-Based Test System," Proc. IEEE Int'l SOC Conf. (SOCC 07), IEEE Press, 2007, pp. 225-228.
8. C.V. Sellathamby et al., "Noncontact Wafer Probe Using Wireless Probe Cards," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 447-452.
9. B. Moore et al., "Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes," Proc. Int'l Test Conf. (ITC 08), IEEE CS Press, 2008, pp. 1-10.
10. J.-M. Lu and C.-W. Wu, "Cost and Benefit Models for Logic and Memory BIST," Proc. Design, Automation and Test in Europe Conf. (DATE 00), ACM Press, 2000, pp. 710-714.
11. R.-F. Huang, C.-H. Chen, and C.-W. Wu, "Economic Aspects of Memory Built-in Self-Repair," IEEE Design & Test, vol. 24, no. 2, 2007, pp. 164-172.
12. P.K. Nag et al., "Modeling the Economics of Testing: A DFT Perspective," IEEE Design & Test, vol. 19, no. 1, 2002, pp. 29-41.

Index Terms:
design and test, wireless testing, test cost model, DFT, HOY, cost estimation
YuTsao Hsing, LiMing Denq, Chao-Hsun Chen, Cheng-Wen Wu, "Economic Analysis of the HOY Wireless Test Methodology," IEEE Design & Test of Computers, vol. 27, no. 3, pp. 20-30, May-June 2010, doi:10.1109/MDT.2009.96
Usage of this product signifies your acceptance of the Terms of Use.