This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Power Supply Noise: A Survey on Effects and Research
March/April 2010 (vol. 27 no. 2)
pp. 51-67
ASCII Text
x 
 
Mohammad Tehranipoor, Kenneth M. Butler, "Power Supply Noise: A Survey on Effects and Research," IEEE Design & Test of Computers, vol. 27, no. 2, pp. 51-67, March/April, 2010.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2010.52,
author = {Mohammad Tehranipoor and Kenneth M. Butler},
title = {Power Supply Noise: A Survey on Effects and Research},
journal ={IEEE Design & Test of Computers},
volume = {27},
number = {2},
issn = {0740-7475},
year = {2010},
pages = {51-67},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2010.52},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Power Supply Noise: A Survey on Effects and Research
IS - 2
SN - 0740-7475
SP51
EP67
EPD - 51-67
A1 - Mohammad Tehranipoor,
A1 - Kenneth M. Butler,
PY - 2010
KW - design and test
KW - power supply noise (PSN)
KW - path delay testing
KW - transition delay fault testing
KW - timing analysis
VL - 27
JA - IEEE Design & Test of Computers
ER -
 
Mohammad Tehranipoor, University of Connecticut, Storrs
Kenneth M. Butler, Texas Instruments

As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuit's noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis.

1. M. Nourani and A. Radhakrishnan, "Power-Supply Noise in SoCs: ATPG, Estimation and Control," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 507-516.
2. M. Nourani, M. Tehranipoor, and N. Ahmed, "Pattern Generation and Estimation for Power Supply Noise Analysis," Proc. 23rd VLSI Test Symp. (VTS 05), IEEE CS Press, 2005, pp. 439-444.
3. J. Savir, "Skewed-Load Transition Test: Part I, Calculus," Proc. Int'l Test Conf. (ITC 92), IEEE CS Press, 1992, pp. 705-713.
4. N. Ahmed et al., "Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers," IEEE Trans. Computer-Aided Design, vol. 26, no. 5, 2007, pp. 896-906.
5. J. Savir and S. Patil, "On Broad-Side Delay Test," Proc. 12th VLSI Test Symp. (VTS 94), IEEE CS Press, 1994, pp. 284-290.
6. B. Dervisoglu and G. Stong, "Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement," Proc. Int'l Test Conf. (ITC 91), IEEE CS Press, 1991, pp. 365-374.
7. J. Rearick and R. Rodgers, "Calibrating Clock Stretch during AC Scan Testing," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 266-273.
8. Y.-S. Chang, S.K. Gupta, and M.A. Breuer, "Analysis of Ground Bounce in Deep Sub-micron Circuits," Proc. 15th VLSI Test Symp. (VTS 97), IEEE CS Press, 1997, pp. 110-116.
9. A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, "On-Die Droop Detector for Analog Sensing of Power Supply Noise," J. Solid-State Circuits, vol. 39, no. 4, 2004, pp. 651-660.
10. Z. Abuhamdeh et al., "A Production IR-Drop Screen on a Chip," IEEE Design & Test, vol. 24, no. 3, 2007, pp. 216-224.
11. J. Saxena et al., "A Case Study of IR-Drop in Structured At-Speed Testing," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, pp. 1098-1104.
12. N. Ahmed, M. Tehranipoor, and V. Jayaram, "Supply Voltage Noise Aware ATPG for Transition Delay Faults," Proc. 25th VLSI Test Symp. (VTS 07), IEEE CS Press, 2007, pp. 179-186.
13. J. Lee et al., "Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation," Proc. Design, Automation and Test in Europe Conf. (DATE 08), IEEE CS Press, pp. 1172-1177.
14. N. Ahmed, M. Tehranipoor, and V. Jayaram, "Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SoC Design," Proc. 44th Design Automation Conf. (DAC 07), IEEE CS Press, 2007, pp. 533-538.
15. A. Kokrady and C.P. Ravikumar, "Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures," Proc. 17th Int'l Conf. VLSI Design (VLSID 04), IEEE CS Press, 2004, pp. 597-602.
16. J. Wang et al., "Modeling Power Supply Noise in Delay Testing," IEEE Design & Test, vol. 24, no. 3, 2007, pp. 226-234.
17. S. Remersaro et al., "Scan-Based Tests with Low Switching Activity," IEEE Design & Test, vol. 24, no. 3, 2007, pp. 268-275.
18. X. Wen et al., "On Low-Capture-Power Test Generation for Scan Testing," Proc. 23rd VLSI Test Symp. (VTS 05), IEEE CS Press, 2005, pp. 265-270.
19. X. Wen et al., "A New ATPG Method for Efficient Capture Power Reduction during Scan Testing," Proc. IEEE VLSI Test Symp. (VTS 06), IEEE CS Press, 2006, pp. 58-65.
20. N. Ahmed, M. Tehranipoor, and V. Jayaram, "A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), IEEE CS Press, 2006, pp. 198-203.
21. A. Krstic, Y.-M. Jiang, and K.T. Cheng, "Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power-Supply Noise Effects," IEEE Trans. Computer-Aided Design, vol. 20, no. 3, 2001, pp. 416-425.
22. Y.-M. Jiang and K.-T. Cheng, "Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices," Proc. 36th Design Automation Conf. (DAC 99), IEEE CS Press, 1999, pp. 760-765.
23. J.-J. Liou et al., "Modeling, Testing, and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices," IEEE Trans. Computer-Aided Design, vol. 22, no. 6, 2003, pp. 756-769.
24. S. Pant et al., "Vectorless Analysis of Supply Noise Induced Delay Variation," Proc. Int'l Conf. Computer-Aided Design (ICCAD 03), IEEE CS Press, 2003, pp. 184-191.
25. G. Bai, S. Bodda, and I.N. Hajj, "Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits," Proc. 38th Design Automation Conf. (DAC 01), IEEE CS Press, pp. 295-300.
26. R. Ahmadi and F.N. Najm, "Timing Analysis in Presence of Power Supply and Ground Voltage Variations," Proc. Int'l Conf. Computer-Aided Design (ICCAD 03), IEEE CS Press, 2003, pp. 176-183.
27. K. Arabi, R. Saleh, and X. Meng, "Power Supply Noise in SoCs: Metrics, Management, and Measurement," IEEE Design & Test, vol. 24, no. 3, 2007, pp. 236-244.
28. Y.-M. Jiang, K.-T. Cheng, and A. Krstic, "Estimation of Maximum Power and Instantaneous Current Using A Genetic Algorithm," Proc. IEEE Custom Integrated Circuits Conf. (CICC 97), IEEE Press, 1997, pp. 135-138.
29. I. Polian et al., "Power Droop Testing," IEEE Design & Test, vol. 24, no. 3, 2007, pp. 276-284.
30. J. Ma, J. Lee, and M. Tehranipoor, "Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths," Proc. IEEE VLSI Test Symp. (VTS 09), IEEE CS Press, 2009, pp. 221-226.

Index Terms:
design and test, power supply noise (PSN), path delay testing, transition delay fault testing, timing analysis
Citation:
Mohammad Tehranipoor, Kenneth M. Butler, "Power Supply Noise: A Survey on Effects and Research," IEEE Design & Test of Computers, vol. 27, no. 2, pp. 51-67, March-April 2010, doi:10.1109/MDT.2010.52
Usage of this product signifies your acceptance of the Terms of Use.