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| Xi-Wei Lin, Victor Moroz, "Layout Proximity Effects and Modeling Alternatives for IC Designs," IEEE Design & Test of Computers, vol. 27, no. 2, pp. 18-25, March/April, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2010.48, author = {Xi-Wei Lin and Victor Moroz}, title = {Layout Proximity Effects and Modeling Alternatives for IC Designs}, journal ={IEEE Design & Test of Computers}, volume = {27}, number = {2}, issn = {0740-7475}, year = {2010}, pages = {18-25}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2010.48}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Layout Proximity Effects and Modeling Alternatives for IC Designs IS - 2 SN - 0740-7475 SP18 EP25 EPD - 18-25 A1 - Xi-Wei Lin, A1 - Victor Moroz, PY - 2010 KW - CMOS KW - compact model KW - design and test KW - extraction KW - layout KW - lithography KW - mobility KW - proximity KW - stress KW - threshold voltage KW - variability VL - 27 JA - IEEE Design & Test of Computers ER - | |||
Layout-dependent variations significantly affect device modeling, model extraction, and design solutions. A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation.
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