Chip designers today have to account for process variations in nanometer CMOS technology. Innovations in manufacturing processes alone are no longer sufficient to mitigate the adverse effects of process variations. The need of the hour is to develop accurate, but tractable and compact, variability models that can handle spatial and temporal aspects of process variations.

This timely special issue on compact variability modeling for nanometer CMOS technology presents the IEEE Design & Test readership with tutorial material, research advances, practical experiences, and perspectives on future trends. Guest Editors Frank Liu and Yu (Kevin) Cao have done a great job in putting together this special issue with five selected articles. I thank Frank, Kevin, and all the authors for their contributions, and I hope you will enjoy reading the special issue.

This issue also includes a survey article, "Power Supply Noise: A Survey on Effects and Research," by Mohammad Tehranipoor and Kenneth Butler. For technology nodes at 32 nm and below, power supply noise is a major contributor to the degradation of circuit performance. This article presents an overview of low-power testing and delay test techniques; in addition, the article surveys ongoing research activities in academia and industry for analyzing power supply noise and dealing with its effects during delay test and timing analysis.

A special perspectives article on the past, present, and future of electronic design automation (EDA) is also included in this issue. This article is in the form of a report—"NSF Workshop on EDA: Past, Present, and Future (Part 1)"—which is based on a National Science Foundation workshop on this topic held in July 2009. The document is both restrospective and forward-looking, and it should especially appeal to the Design & Test readership. Jason Cong and Robert Brayton have prepared the report in two parts, and the first part is being published in this issue. You can look forward to Part 2 of this report in the May/June issue.

Elsewhere in this issue, we have included a one-page report summary of highlights from both HLDVT 2009 and part 2 of the ITC 2009 panel summaries. For the full versions of reports and panel summaries, see http://www.computer.org/dt/conf_reports and http://www.computer.org/dt/panel_summaries. Readers will also find our regular Book Reviews and The Last Byte departments. Grant Martin reviews the recently published Embedded System Design: Modeling, Synthesis and Verification by Daniel D. Gajski, Samar Abdi, Andreas Gerstlauer, and Gunar Schirner. This book is a timely introduction to embedded-systems design methodologies and tools. In The Last Byte, Sani Nassif takes a swipe at the complexity of today's models for ICs and makes an eloquent case for simplicity in modeling and analysis.

In forthcoming issues, D&T will publish columns by Andrew Kahng (The Road Ahead), and an update from Jeff Rearick on IEEE standards activities in design and test. We have also started a new Tutorials department, under the leadership of Dimitris Gizopoulos, and we plan to publish two tutorial articles in 2010.

Krishnendu Chakrabarty

Editor in Chief

IEEE Design & Test