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The fate of stacking
September/October 2009 (vol. 26 no. 5)
pp. 112
David S. Kung, IBM T.J. Watson Research Center

The impending doom of CMOS scaling has semiconductor mavericks scrambling for alternative solutions to continue increasing the device density per chip. One serious candidate is 3D integration in which the planar manufacturing technology extends skyward into the third dimension, much like skyscrapers. Similarities between chip architecture and building architecture are plentiful, and the author draws some parallels between the two.

Index Terms:
3D IC, design and test, stacking, CMOS scaling
Citation:
David S. Kung, "The fate of stacking," IEEE Design & Test of Computers, vol. 26, no. 5, pp. 112, Sept.-Oct. 2009, doi:10.1109/MDT.2009.127
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