Issue No.05 - September/October (2009 vol.26)
Published by the IEEE Computer Society
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.126
<p>This month's Test Technology TC Newsletter reviews the July 2009 2nd IEEE Workshop on Hardware-Oriented Security and Trust, and features upcoming events for November 2009: 40th International Test Conference, 18th Asian Test Symposium, and 10th IEEE Workshop on RTL and High-Level Testing.</p>
Past TTTC Events
2nd IEEE Workshop on Hardware-Oriented Security and Trust (HOST 09)
27 July 2009
San Francisco, California
The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits. The HOST 2009 keynote speech was given by Paul Kocher, president and Chief Scientist of Cryptography Research, San Francisco, California. A total of 13 papers and 4 poster presentations were presented at this year's event. (HOST 2010 will be held in conjunction with DAC 2010.)
Upcoming TTTC Events
40th International Test Conference (ITC 09)
1–6 November 2009
The International Test Conference is the world's premier conference dedicated to the electronic test of devices, boards, and systems. ITC covers the complete test cycle from design verification, test, diagnosis, failure analysis, and back to process and design improvement. The conference will focus on adaptive test, built-in self-test, low-cost ATE, RF test, test data analysis, and many more topics.
18th Asian Test Symposium (ATS 09)
23–26 November 2009
The Asian Test Symposium (ATS) provides an open forum for researchers and engineers from countries all over the world, especially from Asia, to exchange innovative ideas on system, board, and device testing with design, manufacturing, and field considerations in mind.
10th IEEE Workshop on RTL and High-Level Testing (WRTLT 09)
27–28 November 2009
The Chinese University of Hong Kong
Hong Kong SAR, China
WRTLT 09 provides an ideal forum for discussions on important topics such as functional fault modeling, microprocessor testing, RTL ATPG, RTL BIST, the relationship between RTL and gate-level testing, design verification, high-level test bench generation, and SoC testing.
Newsletter Editor's Invitation
I would appreciate input and suggestions about the newsletter from the test community. Please forward your ideas; contributions; and information on awards, conferences, and workshops to Mohammad Tehranipoor, Electrical and Computer Engineering Department, Univ. of Connecticut, 371 Fairfield Way, Storrs, CT 06269-2157; tehrani@ engr.uconn.edu.
Editor, TTTC Newsletter