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Issue No.05 - September/October (2009 vol.26)
pp: 92-104
Hao Yu , Berkeley Design Automation
Lei He , University of California, Los Angeles
Mau-Chung Frank Chang , University of California, Los Angeles
ABSTRACT
<p>Existing shield insertion for multiple signal nets can lead to a nonuniformly distributed, capacitive-coupling length and inductive return paths, introducing large delays and delay variation by crosstalk. This article discusses a twisted, staggered interconnect structure that reduces both inductive and capacitive crosstalk. The proposed design reduces delay by 25% and reduces delay variation by 25&#x00D7; compared to designs employing coplanar shields.</p>
INDEX TERMS
on-chip signaling, crosstalk reduction, shield insertion, interconnect structure, chip multiprocessors
CITATION
Hao Yu, Lei He, Mau-Chung Frank Chang, "Robust On-Chip Signaling by Staggered and Twisted Bundle", IEEE Design & Test of Computers, vol.26, no. 5, pp. 92-104, September/October 2009, doi:10.1109/MDT.2009.121
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