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Multidimensional Test Escape Rate Modeling
September/October 2009 (vol. 26 no. 5)
pp. 74-82
Kenneth M. Butler, Texas Instruments
John M. Carulli Jr., Texas Instruments
Jayashree Saxena, Texas Instruments
Amit Nahar, Texas Instruments
W. Robert Daasch, Portland State University

Editor's note:

Today's SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented.

—Nur A. Touba, University of Texas

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Index Terms:
Defect level, defective parts per million (DPPM), design and test, test escapes, yield, fault coverage
Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena, Amit Nahar, W. Robert Daasch, "Multidimensional Test Escape Rate Modeling," IEEE Design & Test of Computers, vol. 26, no. 5, pp. 74-82, Sept.-Oct. 2009, doi:10.1109/MDT.2009.118
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