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Issue No.05 - September/October (2009 vol.26)
pp: 63
Published by the IEEE Computer Society
With the well-known trend of continued CMOS scaling, traditional on-chip interconnect systems are projected to soon reach the point of having a very limited ability to meet the performance needs and specifications of ICs and SoCs. According to the International Technology Roadmap for Semiconductors, material innovation with traditional scaling will, over the longer term, no longer satisfy performance requirements and new interconnect paradigms will be needed. In other words, with technology scaling, dependence on traditional materials innovation alone will lead to a brick wall, which only radically different interconnect architectures will be able to overcome. Innovative interconnect paradigms based on optical technologies, RF/wireless methods, and carbon nanotubes are promising alternatives that may indeed overcome the challenges presented. These new technologies typically offer new degrees of freedom with potentially significant impact on interconnect design, routing, delay, and power dissipation. Other challenges include problems of reliability and developing adequate CAD tools.
IEEE Design and Test seeks original manuscripts for a special issue on Emerging Interconnect Technologies for Gigascale Integration, scheduled for publication in July/August 2010. While bridging the gap between various disciplines, this special issue will highlight new interconnect paradigms and present some of their features, advantages, disadvantages, and associated challenges. Topics of interest include (but are not limited to)

    • Optical Interconnects as on-chip communication channels

    • RF transmission line-based interconnect fabrics

    • On-chip and short-range wireless links for VLSI

    • Carbon nanotubes (CNT)-based interconnects

    • Characteristics of multicore chips incorporating various emerging interconnects as overall communication backbones

    • Design of CAD tools facilitating design with new interconnect paradigms

    • Test and reliability issues arising out of the radically different interconnects

Submission and review procedures
Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at https://mc.manuscriptcentral.com/cs-ieee. Indicate that you are submitting your article to the special issue on "Emerging Interconnect Technologies for Gigascale Integration." All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 200 words) and a maximum of 12 References (50 for surveys). This amounts to about 4,000 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, passive to active voice, logical organization, readability, and adherence to style. Please see IEEE D&T Author Resources at http://www.computer.org/dt/author.htm, then scroll down and click on Author Center for submission guidelines and requirements.
Schedule

    • Articles due for review: 15 November 2009

    • Reviews completed: 1 February 2010

    • Article revisions due: 15 March 2010

    • Notice of final acceptance: 10 April 2010

    • Materials due for edit: 20 April 2010

Questions?
Please direct questions regarding this special issue to Guest Editors Partha Pande (pande@eecs.wsu.edu) and Sriram Vangal (sriram.r.vangal@intel.com).
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