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Issue No.05 - September/October (2009 vol.26)
pp: 36-47
Jibang Liu , Rensselaer Polytechnic
Nanning Zheng , Xi'an Jiaotong University
Jian-Qiang Lu , Rensselaer Polytechnic
Kenneth Rose , Rensselaer Polytechnic
Hongbin Sun , Xi'an Jiaotong University
<p>Editor's note:</p><p>From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture.</p><p align="right"><it>&#x2014;Yuan Xie, Pennsylvania State University</it></p>
3D integration, design and test, multicore, DRAM, memory hierarchy
Jibang Liu, Rakesh S. Anigundi, Nanning Zheng, Jian-Qiang Lu, Kenneth Rose, Hongbin Sun, "3D DRAM Design and Application to 3D Multicore Systems", IEEE Design & Test of Computers, vol.26, no. 5, pp. 36-47, September/October 2009, doi:10.1109/MDT.2009.105
1. C.C. Liu et al., "Bridging the Processor-Memory Performance Gap with 3D IC Technology," IEEE Design &Test, vol. 22, no. 6, 2005, pp. 556-564.
2. T. Kgil et al., "PicoServer: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocessor," Proc. 12th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 06), ACM Press, 2006, pp. 117-128.
3. G. Loh, Y. Xie, and B. Black, "Processor Design in 3D Die-Stacking Technologies," IEEE Micro, vol. 27, no. 3, 2007, pp. 31-48.
4. G. Loh, "3D-Stacked Memory Architecture for Multi-core Processors," Proc. 35th ACM/IEEE Int'l Symp. Computer Architecture (ISCA 08), IEEE CS Press, 2008, pp. 453-464.
5. B. Black et al., "Die Stacking (3D) Microarchitecture," Proc. Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE CS Press, 2006, pp. 469-479.
6. Tezzaron Semiconductors, "3D Stacked DRAM/Bi-STAR Overview," 2008; .
7. CACTI: An Integrated Cache and Memory Access Time, Cycle Time, Area, Leakage, and Dynamic Power Model,
8. N.L. Binkert et al., "The M5 Simulator: Modeling Networked Systems," IEEE Micro, vol. 26, no. 4, 2006, pp. 52-60.
9. Y.-F. Tsai et al., "Design Space Exploration for 3-D Cache," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 4, 2008, pp. 444-455.
10. M. Ghosh and H.-H.S. Lee, "Smart Refresh: An Enhanced memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs," Proc. 40th ACM/IEEE Int'l Symp. Microarchitecture, IEEE CS Press, 2007, pp. 134-145.
11. J. Barth et al., "A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier," IEEE J. Solid-State Circuits, Jan. 2008, pp. 86-95.
12. K. Albayraktaroglu et al., "Biobench: A Benchmark Suite of Bioinformatics Applications," Proc. Int'l Symp. Performance Analysis of Systems and Software, IEEE CS Press, 2005, pp. 2-9.
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