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Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity
September/October 2009 (vol. 26 no. 5)
pp. 15-25
Pingqiang Zhou, University of Minnesota, Twin Cities
Karthikk Sridharan, University of Minnesota, Twin Cities
Sachin S. Sapatnekar, University of Minnesota, Twin Cities

Editor's note:

This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs–based method to optimize the power grid design.

—Yuan Xie, Pennsylvania State University

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Index Terms:
decoupling capacitors, design and test, MIM decap, CMOS decap, power grid, 3D integration
Citation:
Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar, "Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity," IEEE Design & Test of Computers, vol. 26, no. 5, pp. 15-25, Sept.-Oct. 2009, doi:10.1109/MDT.2009.120
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