The Community for Technology Leaders
RSS Icon
Issue No.05 - September/October (2009 vol.26)
pp: 15-25
Karthikk Sridharan , University of Minnesota, Twin Cities
Sachin S. Sapatnekar , University of Minnesota, Twin Cities
<p>Editor's note:</p><p>This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs&#x2013;based method to optimize the power grid design.</p><p align="right"><it>&#x2014;Yuan Xie, Pennsylvania State University</it></p>
decoupling capacitors, design and test, MIM decap, CMOS decap, power grid, 3D integration
Karthikk Sridharan, Sachin S. Sapatnekar, "Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity", IEEE Design & Test of Computers, vol.26, no. 5, pp. 15-25, September/October 2009, doi:10.1109/MDT.2009.120
1. D. Roberts et al., "Application of On-Chip MIM Decoupling Capacitor for 90nm SOI Microprocessor," Proc. IEEE Int'l Electron Devices Meeting, IEEE Press, 2005, pp. 72-75.
2. Y.L. Tu et al., "Characterization and Comparison of High-kMetal-Insulator-Metal (MiM) Capacitors in 0.13μm Cu BEOL for Mixed-Mode and RF Applications," Proc. IEEE Int'l Symp. VLSI Circuits, IEEE Press, 2003, pp. 79-80.
3. H. Sanchez et al., "Increasing Microprocessor Speed by Massive Application of On-Die High-kMIM Decoupling Capacitors," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 06), IEEE Press, 2006, pp. 2190-2199.
4. H. Su, S.S. Sapatnekar, and S.R. Nassif, "An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts," Proc. Int'l Symp. Physical Design, ACM Press, 2002, pp. 68-73.
5. H.H. Chen and D.D. Ling, "Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design," Proc. 34th Design Automation Conf. (DAC 97), ACM Press, 1997, pp. 638-643.
6. E. Wong, J. Minz, and S.K. Lim, "Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), IEEE CS Press, 2006, pp. 395-400.
7. J.R. Minz, S.K. Lim, and C.-K. Koh, "3D Module Placement for Congestion and Power Noise Reduction," Proc. Great Lakes Symp. VLSI, ACM Press, 2005, pp. 458-461.
8. G. Huang et al., "Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication," Proc. IEEE Electrical Performance of Electronic Packaging Meeting, IEEE Press, 2007, pp. 205-208.
9. P. Zhou et al., "3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 07), IEEE Press, 2007, pp. 590-597.
10. J. Lou et al., "Estimating Routing Congestion Using Probabilistic Analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, 2002, pp. 32-41.
11. B. Goplen and S.S. Sapatnekar, "Placement of 3D ICs with Thermal and Interlayer via Considerations," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 626-631.
12. "Predictive Technology Model," Device Group at Arizona State University; available at
47 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool