|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Philip Emma, Eren Kursun, "Opportunities and Challenges for 3D Systems and Their Design," IEEE Design & Test of Computers, vol. 26, no. 5, pp. 6-14, September/October, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2009.119, author = {Philip Emma and Eren Kursun}, title = {Opportunities and Challenges for 3D Systems and Their Design}, journal ={IEEE Design & Test of Computers}, volume = {26}, number = {5}, issn = {0740-7475}, year = {2009}, pages = {6-14}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.119}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Opportunities and Challenges for 3D Systems and Their Design IS - 5 SN - 0740-7475 SP6 EP14 EPD - 6-14 A1 - Philip Emma, A1 - Eren Kursun, PY - 2009 KW - 3D systems VL - 26 JA - IEEE Design & Test of Computers ER - | |||
Editor's note:
This article presents the system design opportunities offered by 3D integration, and it discusses the design and test challenges for 3D ICs, with various new design-for-manufacture and DFT issues.
—Yuan Xie, Pennsylvania State University
1. K. Bernstein et al., "Interconnects in the Third Dimension: Design Challenges for 3D ICs," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 562-567.
2. P. Emma and E. Kursun, "Is 3D Integration the Next Growth Engine after Moore's Law, or Is It Different?" IBM J. Research and Development, vol. 01.52, no. 6, 2008, pp. 541-552.
3. E. Beyne, "3D Interconnection and Packaging: Impending Reality or Still a Dream?" Proc. IEEE Int'l Solid State Circuits Conf. (ISSCC 04), IEEE CS Press, 2004, pp. 554-559.
4. K. Banerjee et al., "3D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," Proc. IEEE, IEEE Press, 2001, pp. 602-633.
5. P. Leduc et al., "Enabling Technologies for 3D Chip Stacking," Proc. IEEE Very Large Scale Integration (VLSI) Technology Systems and Applications, IEEE CS Press, 2008, pp. 76-78.
6. R. Reif et al., "Fabrication Technologies for Three- Dimensional Integrated Circuits," Proc. IEEE Int'l Symp. Quality-Aware Electronic Design, IEEE CS Press, 2002, pp. 33-37.
7. K. Ruhmer et al., "Lead-Free Micro-Bumping Cost and Yield Challenges," Proc. IEEE Electronics Packaging Technology Conf., IEEE CS Press, 2007, pp. 331-337.
8. N. Swinnen et al., "3D Integration by Cu-Cu Thermo-Compression Bonding of Extremely Thinned Bulk-Si Die Containing 10 μm Pitch Through-Si Vias," Proc. IEEE Int'l Electron Devices Meeting (IEDM 06), IEEE CS Press, 2006, pp. 1-4.
9. G. Huang et al., "Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implications," Proc. IEEE Electrical Performance of Electronic Packaging, IEEE CS Press, 2007, pp. 205-208.
10. C. Patel et al., "Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver," Proc. IEEE Electronic Components and Technology Conf., IEEE CS Press, 2005, pp. 1318-1324.
11. X. Wu, P. Falkenstern, and Y. Xie, "Scan Chain Design for Three-Dimensional Integrated Circuits (3D ICs)," Proc. IEEE Int'l Conf. Computer Design, IEEE CS Press, 2007, pp. 208-214.
12. B. Black et al., "Die Stacking Microarchitecture," Proc. Int'l Symp. Microarchitecture, ACM Press, 2006, pp. 469-479.
13. Y. Liu et al., "Fine-Grain 3D Integration for Microarchitecture Design through Cube Packing Exploration," Proc. IEEE/ACM Int'l Conf. Computer Design, IEEE CS Press, 2007, pp. 259-266.

