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September/October 2009 (vol. 26 no. 5)
pp. 4-5
Yuan Xie, Pennsylvania State University

Interest in 3D integration is being renewed as researchers face challenges from the complexities, and cost, of scaling to 22 nm and beyond. Innovative device structures such as finFET, and extremely thin fully depleted silicon-on-insulator (ETSOI), must be deployed to continue scaling. Even with those structures, however, customary performance gains can no longer be achieved without also incurring an unacceptable increase in power. The cost of technology development in the nanoscale domain can run into the billions because massive lithographic retooling is required to cross the 22-nm barrier. The chip industry, therefore, is actively pursuing 3D integration as a viable alternative to provide density scaling. This special issue presents four articles on topics addressing some of these challenges.

Index Terms:
22-nm barrier, 3D IC, 3D integration, design and test, density scaling
Citation:
David S. Kung, Yuan Xie, "Guest Editors' Introduction: Opportunities and Challenges of 3D Integration," IEEE Design & Test of Computers, vol. 26, no. 5, pp. 4-5, Sept.-Oct. 2009, doi:10.1109/MDT.2009.115
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