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| "Stacking chips in 3D," IEEE Design & Test of Computers, vol. 26, no. 5, pp. 2, September/October, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2009.122, author = {}, title = {Stacking chips in 3D}, journal ={IEEE Design & Test of Computers}, volume = {26}, number = {5}, issn = {0740-7475}, year = {2009}, pages = {2}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.122}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Stacking chips in 3D IS - 5 SN - 0740-7475 SP EP EPD - 2 PY - 2009 KW - 3D IC design and test KW - integration KW - interconnect-delay bottleneck VL - 26 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.122
3D IC solutions have been developed for several different reasons: to reduce the system form factor for portable platforms; to increase system performance by alleviating the interconnect-delay bottleneck; and to manage overall system cost by stacking heterogeneous chips, rather than integrate diverse system components into a single chip through 2D scaling. However, although some 3D IC markets are emerging, and most technical issues of 3D integration are almost solved, several thermal and production-test challenges remain as obstacles. This special issue of
Index Terms:
3D IC design and test, integration, interconnect-delay bottleneck
Citation:
"Stacking chips in 3D," IEEE Design & Test of Computers, vol. 26, no. 5, pp. 2, Sept.-Oct. 2009, doi:10.1109/MDT.2009.122
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