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Issue No.05 - September/October (2009 vol.26)
pp: 2
ABSTRACT
<p>3D IC solutions have been developed for several different reasons: to reduce the system form factor for portable platforms; to increase system performance by alleviating the interconnect-delay bottleneck; and to manage overall system cost by stacking heterogeneous chips, rather than integrate diverse system components into a single chip through 2D scaling. However, although some 3D IC markets are emerging, and most technical issues of 3D integration are almost solved, several thermal and production-test challenges remain as obstacles. This special issue of <it>IEEE Design &#x0026; Test</it> takes a look a those issues.</p>
INDEX TERMS
3D IC design and test, integration, interconnect-delay bottleneck
CITATION
"Stacking chips in 3D", IEEE Design & Test of Computers, vol.26, no. 5, pp. 2, September/October 2009, doi:10.1109/MDT.2009.122
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