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Issue No.04 - July/August (2009 vol.26)
pp: 78-87
Yuan Xie , Pennsylvania State University
Yibo Chen , Pennsylvania State University
ABSTRACT
<p>Editor's note:</p><p>CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys recent progress in the statistical high-level synthesis area.</p><p>&#x2014;Philippe Coussy, Universit&#x00E9; de Bretagne-Sud</p>
INDEX TERMS
statistical high-level synthesis, design and test, process variation, parametric yield
CITATION
Yuan Xie, Yibo Chen, "Statistical High-Level Synthesis under Process Variability", IEEE Design & Test of Computers, vol.26, no. 4, pp. 78-87, July/August 2009, doi:10.1109/MDT.2009.85
REFERENCES
1. C. Kenyon et al., "Managing Process Variation in Intel's 45nm CMOS Technology," Intel Technology J., vol. 12, no. 2, 2008; http://www.intel.com/technology/itj/2008/ v12i2/3-managing1-abstract.htm.
2. A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Springer, 2005.
3. P. Coussy and A. Morawiec, High-Level Synthesis: From Algorithm to Digital Circuit, Springer, 2008.
4. F. Wang, G. Sun, and Y. Xie, "A Variation Aware High Level Synthesis Framework," Proc. IEEE Design, Automation and Test in Europe Conf. (DATE 08), IEEE CS Press, 2008, pp. 1063-1068.
5. W.-L. Hung, X. Wu, and Y. Xie, "Guaranteeing Performance Yield in High-Level Synthesis," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), IEEE CS Press, 2006, pp. 303-309.
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7. Y. Chen, J. Ouyang, and Y. Xie, "ILP-Based Scheme for Timing Variation-Aware Scheduling and Resource Binding," Proc. IEEE Int'l SOC Conf., IEEE Press, 2008, pp. 17-30.
8. F. Wang, A. Takach, and Y. Xie, "Variation-Aware Resource Sharing and Binding in Behavioral Synthesis," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 09), IEEE Press, 2009, pp. 79-84.
9. G. Lucas, S. Cromar, and D. Chen, "FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 09), IEEE Press, 2009, pp. 61-66.
10. Y. Chen and Y. Xie, "Tolerating Process Variations in High-Level Synthesis Using Transparent Latches," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 09), IEEE Press, 2009, pp. 73-78.
11. W. Yang, I. Park, and C. Kyung, "Low-Power High-Level Synthesis Using Latches," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 01), ACM Press, 2001, pp. 462-466.
12. F. Wang, X. Wu, and Y. Xie, "Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning," Proc. Conf. Asia and South Pacific Design Automation (ASP-DAC 08), IEEE CS Press, 2008, pp. 2-9.
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