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Issue No.04 - July/August (2009 vol.26)
pp: 68-77
María Carmen Molina , Complutense University of Madrid
Rafael Ruiz-Sautua , Complutense University of Madrid
Alberto Del Barrio , Complutense University of Madrid
José Manuel Mendías , Complutense University of Madrid
ABSTRACT
<p>Editor's note:</p><p>This article presents an original high-level synthesis approach that addresses the problem of dynamic power consumption in data-dominated applications. The proposed scheduling and binding algorithms deal with the switching-activity information, at the variable subword level, to reduce the number of commutations.</p><p align="right">&#x2014;Philippe Coussy, Universit&#x00E9; de Bretagne-Sud</p>
INDEX TERMS
high-level synthesis, design and test, low power, scheduling, binding
CITATION
María Carmen Molina, Rafael Ruiz-Sautua, Alberto Del Barrio, José Manuel Mendías, "Subword Switching Activity Minimization to Optimize Dynamic Power Consumption", IEEE Design & Test of Computers, vol.26, no. 4, pp. 68-77, July/August 2009, doi:10.1109/MDT.2009.86
REFERENCES
1. L. Shang, R.P. Dick, and N.K. Jha, "High-Level Synthesis Algorithms for Power and Temperature Minimization," High-Level Synthesis: From Algorithm to Digital Circuit, P. Coussy, and A. Morawiec eds., Springer, 2008.
2. A. Khanna, and S. McCloud, "Power Exploration in High-Level Synthesis," FPGA and Structured ASIC J., Dec. 2006; http://www.fpgajournal.com/articles_2006 20061219_mentor.htm.
3. X. Xing and C.C. Jonj, "A Look-Ahead Synthesis Technique with Backtracking for Switching Activity Reduction in Low Power High-Level Synthesis," Microelectronics J., vol. 38, nos. 4-5, 2007, pp. 595-605.
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