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Hardware Coprocessor Synthesis from an ANSI C Specification
July/August 2009 (vol. 26 no. 4)
pp. 58-67
Sumit Ahuja, Virginia Polytechnic and State University
Chad Spackman, CebaTech
Sandeep K. Shukla, Virginia Polytechnic and State University

Editor's note:

This article shows how design space exploration can be realized through high-level synthesis. It presents a case study of a hardware implementation of the Advanced Encryption Standard (AES) Rijndael algorithm. Starting from the algorithmic specification, the authors generate various architectures by using the C2R compiler.

—Philippe Coussy, Université de Bretagne-Sud

1. "C2R Compiler," CebaTech; http://cebatech.comc2r_compiler.
2. S. Ahuja, W. Zhang, and S.K. Shukla, A Methodology for Power Aware High-Level Synthesis of Co-Processors from Software Algorithms, tech. report 2008-08, Virginia Polytechnic and State University, Fermat Lab; techreptechrep0808.pdf.
3. J.E. Stine et al., "A Framework for High-Level Synthesis of System-on-Chip Designs," Proc. IEEE Int'l Conf. Microelectronic Systems Education, IEEE CS Press, 2005, pp. 67-68.
4. "GAUT—High-Level Synthesis Tool from C to RTL," Universitéde Bretagne-Sud; http://www-labsticc.univ-ubs.frwww-gaut.
5. E. Simpson et al., "VT Matrix Multiply Design for MEMOCODE '07," Proc. 5th IEEE/ACM Int'l Conf. Formal Methods and Models for Codesign (MEMOCODE 07), IEEE CS Press, pp. 95-96.

Index Terms:
high-level synthesis, design and test, ESL, ASIC, FPGA, ANSI C, Verilog, verification, power reduction, C2R methodology
Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla, "Hardware Coprocessor Synthesis from an ANSI C Specification," IEEE Design & Test of Computers, vol. 26, no. 4, pp. 58-67, July-Aug. 2009, doi:10.1109/MDT.2009.81
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