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Lessons and Experiences with High-Level Synthesis
July/August 2009 (vol. 26 no. 4)
pp. 34-45
Soujanna Sarkar, Texas Instruments
Shashank Dabral, Texas Instruments
Praveen K. Tiwari, Interra Systems
Raj S. Mitra, Texas Instruments

Editor's note:

This article is a designer's perspective on the benefits and challenges of using commercially available HLS tools. The authors have used three such tools for synthesizing industrial ASICs. They discuss their impact on four criteria: design goals, verification closure, ECO handling, and productivity gains.

—Philippe Coussy, Université de Bretagne Sud

1. J. Bier, "Massively Parallel Chips Can Lead to Sticky Software,"22 Apr. 2009; http://www.insidedsp.com/Articles/tabid/ 64/articleType/ArticleView/articleId/308 Default.aspx.

Index Terms:
high-level synthesis, design and test, ESL design, ASIC
Citation:
Soujanna Sarkar, Shashank Dabral, Praveen K. Tiwari, Raj S. Mitra, "Lessons and Experiences with High-Level Synthesis," IEEE Design & Test of Computers, vol. 26, no. 4, pp. 34-45, July-Aug. 2009, doi:10.1109/MDT.2009.84
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