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An Introduction to High-Level Synthesis
July/August 2009 (vol. 26 no. 4)
pp. 8-17
Philippe Coussy, Université de Bretagne-Sud, Lab-STICC
Daniel D. Gajski, University of California
Michael Meredith, Forte Design Systems
Andres Takach, Mentor Graphics

Editor's note:

High-level synthesis raises the design abstraction level and allows rapid generation of optimized RTL hardware for performance, area, and power requirements. This article gives an overview of state-of-the-art HLS techniques and tools.

—Tim Cheng, Editor in Chief

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Index Terms:
high-level synthesis, RTL abstraction, custom processors, hardware synthesis and verification, architectures, design and test
Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andres Takach, "An Introduction to High-Level Synthesis," IEEE Design & Test of Computers, vol. 26, no. 4, pp. 8-17, July-Aug. 2009, doi:10.1109/MDT.2009.69
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