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An Introduction to High-Level Synthesis
July/August 2009 (vol. 26 no. 4)
pp. 8-17
ASCII Text
x 
 
Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andres Takach, "An Introduction to High-Level Synthesis," IEEE Design & Test of Computers, vol. 26, no. 4, pp. 8-17, July/August, 2009.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2009.69,
author = {Philippe Coussy and Daniel D. Gajski and Michael Meredith and Andres Takach},
title = {An Introduction to High-Level Synthesis},
journal ={IEEE Design & Test of Computers},
volume = {26},
number = {4},
issn = {0740-7475},
year = {2009},
pages = {8-17},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - An Introduction to High-Level Synthesis
IS - 4
SN - 0740-7475
SP8
EP17
EPD - 8-17
A1 - Philippe Coussy,
A1 - Daniel D. Gajski,
A1 - Michael Meredith,
A1 - Andres Takach,
PY - 2009
KW - high-level synthesis
KW - RTL abstraction
KW - custom processors
KW - hardware synthesis and verification
KW - architectures
KW - design and test
VL - 26
JA - IEEE Design & Test of Computers
ER -
 
Philippe Coussy, Université de Bretagne-Sud, Lab-STICC
Daniel D. Gajski, University of California
Michael Meredith, Forte Design Systems
Andres Takach, Mentor Graphics

Editor's note:

High-level synthesis raises the design abstraction level and allows rapid generation of optimized RTL hardware for performance, area, and power requirements. This article gives an overview of state-of-the-art HLS techniques and tools.

—Tim Cheng, Editor in Chief

1. A. Sangiovanni-Vincentelli, "The Tides of EDA," IEEE Design &Test, vol. 20, no. 6, 2003, pp. 59-75.
2. D. MacMillen et al., "An Industrial View of Electronic Design Automation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, 2000, pp. 1428-1448.
3. D.W. Knapp, Behavioral Synthesis: Digital System Design Using the Synopsys Behavioral Compiler, Prentice Hall, 1996.
4. J.P. Elliot, Understanding Behavioral Synthesis: A Practical Guide to High-Level Design, Kluwer Academic Publishers, 1999.
5. W. Wolf, "A Decade of Hardware/Software Co-design," Computer, vol. 36, no. 4, 2003, pp. 38-43.
6. H. Chang et al., Surviving the SoC Revolution: A Guide to Platform-Based Design, Kluwer Academic Publishers, 1999.
7. M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Kluwer Academic Publishers, 1998.
8. D. Gajski et al., SpecC: Specification Language and Methodology, Kluwer Academic Publishers, 2000.
9. B. Bailey, G. Martin, and A. Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology, Morgan Kaufman Publishers, 2007.
10. P. Coussy and A. Morawiec eds., High-Level Synthesis: From Algorithm to Digital Circuit, Springer, 2008.
11. D. Ku, and G. De Micheli, High Level Synthesis of ASICs under Timing and Synchronization Constraints, Kluwer Academic Publishers, 1992.
12. D. Gajski et al., High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.
13. R.A. Walker and R. Camposano eds., A Survey of High-Level Synthesis Systems, Springer, 1991
14. S. Gupta et al., SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits, Kluwer Academic Publishers, 2004.
15. A. Orailoglu, and D.D. Gajski, "Flow Graph Representation," Proc. 23rd Design Automation Conf. (DAC 86), IEEE Press, pp. 503-509.
16. M. Girkar and C.D. Polychronopoulos, "Automatic Extraction of Functional Parallelism from Ordinary Programs," IEEE Trans. Parallel and Distributed Systems, vol. 3, no. 2, 1992, pp.166-178.
17. P. Paulin and J.P. Knight, "Algorithms for High-Level Synthesis," IEEE Design and Test, vol. 6, no. 6, 1989, pp. 18-31.
18. M. Reshadi and D. Gajski, "A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths," Proc. Int'l Symp. Hardware/Software Codesign and System Synthesis (CODES+ISSS 05), ACM Press, 2005, pp. 21-26.
19. I. Auge and F. Petrot, "User Guided High Level Synthesis," High-Level Synthesis: From Algorithm to Digital Circuit, P. Coussy, and A. Morawiec eds., Springer, 2008, pp. 171-196.
20. D. Chen, J. Cong, and P. Pan, FPGA Design Automation: A Survey, Now Publishers, 2006.
21. W. Geurts et al., Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications, Kluwer Academic Publishers, 1996.
22. L. Zhong and N.K. Jha, "Interconnect-Aware Low-Power High-Level Synthesis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, 2005, pp. 336-351.
23. M. Kudlur, K. Fan, and S. Mahlke, "Streamroller: Automatic Synthesis of Prescribed Throughput Accelerator Pipelines," Proc. Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS 06), ACM Press, pp. 270-275.
24. M.C. Molina et al., "Area Optimization of Multi-cycle Operators in High-Level Synthesis," Proc. Design, Automation and Test in Europe Conf. (DATE 07), IEEE CS Press, 2007, pp. 1-6.
25. G. Stitt, F. Vahid, and W. Najjar, "A Code Refinement Methodology for Performance-Improved Synthesis from C," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), ACM Press, 2006, pp. 716-723.

Index Terms:
high-level synthesis, RTL abstraction, custom processors, hardware synthesis and verification, architectures, design and test
Citation:
Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andres Takach, "An Introduction to High-Level Synthesis," IEEE Design & Test of Computers, vol. 26, no. 4, pp. 8-17, July-Aug. 2009, doi:10.1109/MDT.2009.69
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