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From the EIC: Building and verifying hardware at a higher level of abstraction
July/August 2009 (vol. 26 no. 4)
pp. 2

To manage design complexity and cost, the next-generation design methodology must enable the highest possible level of abstraction; hide, insofar as possible, implementation details from designers; allow efficient design reuse, including the reuse of IP blocks, underlying architectures, and a large portion of embedded software across multiple generations; and provide flexibility in the system architecture of computation, communications, and storage elements. High-level synthesis is necessary and critical in such a solution. Consequently, this issue of IEEE Design & Test presents nine articles to review the progress of high-level synthesis research and which examine various aspects of this up-and-coming methodology.

Index Terms:
design and test, high-level synthesis, design complexity
Citation:
"From the EIC: Building and verifying hardware at a higher level of abstraction," IEEE Design & Test of Computers, vol. 26, no. 4, pp. 2, July-Aug. 2009, doi:10.1109/MDT.2009.72
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