Issue No.03 - May/June (2009 vol.26)
Published by the IEEE Computer Society
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.52
Elections to Chair in IEEE DATC
We are pleased to announce that David Kung is the next chair of the IEEE Design Automation Technical Committee. DATC, which is involved with computer-oriented techniques in the design process of computer and electronic systems, emphasizes design languages, logic synthesis, verification techniques (including digital simulation), manufacturing interface data, graphics, and database management.
Kung manages a department of design automation researchers and charts the future direction of design tools research for IBM. He joined the Advanced Simulation Group in IBM Research in Yorktown Heights, New York, in 1986 to work on a massively parallel hardware simulation engine. Subsequently, he joined the Logic Synthesis group and was a contributor to IBM's BooleDozer logic synthesis system. In 1999, he became the manager of the Logic Synthesis group and led project management and technical development of Placement Driven Synthesis (PDS), IBM's physical synthesis software. He received a BA from the University of California at Berkeley, an MA from Harvard University, and a PhD from Stanford University.
Please contact Juan-Antonio Carballo (email@example.com) for more information.
CANDE 2009 Workshop
The CANDE (Computer-Aided Network Design) Committee is a technical activity of the IEEE Circuits and Systems Society and IEEE Council on Electronic Design Automation. CANDE, which acts as a working group for electronic computer-aided design, plays a major role in EDA, particularly through the CANDE Predictions and its forward-looking annual workshop, which in 2009 will be held in conjunction with ICCAD, and the CANDE Predictions. The yearly workshop offers an opportunity to discuss advanced issues relevant to the CAD community and brings together practitioners, researchers, and managers from industry and academia. To encourage long-range and open discussion, no proceedings are published and no recordings of sessions are allowed. CANDE community members take an active part in identifying topics and organizing sessions. Planning sessions for the workshop are held at DAC and ICCAD each year. Attendance at the CANDE workshop is open to all EDA/CAD professionals.
In these challenging times, it is especially important for CANDE to gather leaders together from industry and academia to brainstorm the future directions and strategies for the EDA and semiconductor industry. Members of the CAD community are encouraged to contact the chair for more information. Officers for the 2008–2009 term are as follows: Chair: David Pan, firstname.lastname@example.org; Secretary: Subhasish Mitra, email@example.com; Treasurer: Priyank Kalla, firstname.lastname@example.org; Past Chair: Forrest Brewer, email@example.com; Publicity Chair: Lou Scheffer, firstname.lastname@example.org; Workshop Chair: Farinaz Koushanfar, email@example.com.
Visit the CANDE website, http://www.cande.net, for more information.
IDESA: Effective Design at 45 nm
Deep submicron design confronts designers with problems not encountered at larger feature sizes. These problems will affect all designers—digital, analog, and mixed-RF. Many of the problems can be tackled by new processing techniques, but the new techniques have a consequential effect on design. To successfully tape-out any design at deep submicron feature sizes requires an appreciation of these new problems, and rigorous application of the appropriate corrective design techniques.
The IDESA Design for Manufacturing Flow course, to be offered later this spring, provides early insight into these new problems and solutions. Aspects of deep submicron lithography and processing, including yield analysis and defects, will be covered. The course explains which new post-layout manufacturability techniques were developed, why they are needed, and what the effect is on layout. Students will learn to assess the importance of the different process-oriented effects, and how to address them during design and layout. The course will also address the heightened importance of design-for-test. IDESA is a European EC Framework 7 project that has been identified as a support action to help universities follow the fast-paced evolution of IC design and implementation flows for deep submicron technologies. A demo session will be held on yield analysis, and hands-on sessions will be offered on lithography effects and on DFM solutions during layout. The course uses the TSMC 90-nm process as a reference, but the course content is even more applicable at the 65-nm and 45-nm design nodes.
Dates and locations for the IDESA Design for Manufacturing Flow course are as follows:
• 12-15 May—INFN Padova, Italy
• 9-12 June—Czech Technical University, Czech Republic
Sign up for these IDESA courses, along with others in the areas of analog, digital, and RF design, at the IDESA website: http://www.idesa.rl.ac.uk/.
IEEE Embedded Systems Letters (ESL)—Call For Papers
IEEE Embedded Systems Letters seeks to provide a forum for quick dissemination of research results in the domain of embedded systems with a target turn-around time of three months.
Submissions are welcome on any topic in the broad area of embedded systems and embedded software, especially but not limited to:
Architectural and micro-architectural design of embedded systems; design automation algorithms, methods, and tools for VLSI implementations; component modeling and component-based development methodologies; compilation and managed runtime environments for embedded systems; OS, middleware and support systems for embedded system design; low-power design and power management; testing, validation, and verification of embedded software; embedded sensor networks and embedded control systems: design, analysis and application to cyber-physical systems; embedded systems security; applications of embedded systems and software, and so on.
Submitted letters must be four pages or fewer, including all figures, tables, and references. Submissions exceeding this length will be returned without review.
Papers should use 7.875 in × 10.75 in (20 cm × 27.30 cm) trim size and the IEEE Transactions two-column format in 9-pt. font. In word counts, this corresponds to roughly 2,200 words. Submissions to IEEE ESL must consist of original work that has not been previously published nor is currently under review elsewhere.
Please mail manuscripts to firstname.lastname@example.org.
Cadence Design Contest
Cadence EMEA (Europe, Middle East, and Africa) is organizing the first full custom design contest. In this unique and innovative event, the best layout designers from the top academic institutions in Europe compete for the title of "Fastest full custom layout designer of the year."
The rules are simple. On 20 April 2009, participants received by email the schematic of an analog block. The first participant to send a DRC and LVS correct implementation of the schematic back to Cadence wins the top prize. The contest is open to any student registered in an academic program (Bachelor, Master, Phd students are welcome). The winner will be invited to CDNLive! EMEA in Munich, 18-20 May 2009, and receive a coupon for two days of training of their choice.
The award for "Fastest full custom layout designer of the year will" be delivered during the CDNLive! EMEA conference. During the Designer Expo exhibition, the winner will demonstrate their layout skills "live" and have the opportunity to share their best practices with the conference participants.
For more information, visit http://www.cadence.com.
Upcoming CEDA Events
CEDA conferences provide excellent opportunities for those interested in learning about the latest technical trends in electronic design and automation. If you'd like to participate or you have an idea about new topics of interest for our conferences, please contact William Joyner (email@example.com), CEDA vice president of conferences.
7th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)
13–15 July 2009
46th Design Automation Conference (DAC)
26–31 July 2009
9th International Forum on Application-Specific Multiprocessor SoC (MPSoC)
2–7 August 2009
19th International Workshop on Power and Timing Modeling, Optimization, and Simulation (PATMOS)
9–11 September 2009
International Conference on Hardware/ Software Codesign and System Synthesis (CODES+ISSS)
11–16 October 2009
4th International Conference on Nano Networks (Nano-Net)
18–20 October 2009
IEEE/ACM 2009 International Conference on Computer-Aided Design (ICCAD)
2–5 November 2009
San Jose, California
Formal Methods in Computer-Aided Design Conference (FMCAD)
15–18 November 2009