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Issue No.03 - May/June (2009 vol.26)
pp: 70-77
Ishwar Parulkar , Sun Microsystems
Babu Turumella , Sun Microsystems
<p>This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.</p>
verification, test generation, design and test, multithreaded processors, server chipset, debug, SerDes, CMT Sparc microprocessor, RAS
Ishwar Parulkar, Babu Turumella, "Comprehensive Approach to High-Performance Server Chipset Debug", IEEE Design & Test of Computers, vol.26, no. 3, pp. 70-77, May/June 2009, doi:10.1109/MDT.2009.53
1. J. Bhadra et al., "A Survey of Hybrid Techniques for Functional Verification," IEEE Design &Test, vol. 24, no. 2, 2007, pp. 112-122.
2. A. Carbine and D. Feltham, "Pentium Pro Processor Design for Test and Debug," IEEE Design and Test, vol. 15, no. 3, 1998, pp. 294-303.
3. A.B.T. Hopkins and K.D. McDonald-Maier, "Debug Support Strategy for System-on-Chips with Multiple Processor Cores," IEEE Trans. Computers, vol. 55, no. 2, 2006, pp. 174-184.
4. A.B.T. Hopkins and K.D. McDonald-Maier, "Debug Support for Complex Systems on Chip: A Review," IEEE Proc. Computers, vol. 153, no. 4, 2006, pp. 197-207.
5. Y.-C.S. Chen, D. Lu, and G. Yuan, "Post-Silicon Design Methodology on Chip Power Characterization, Validation, and Debug Applied on High Performance per Watt Microprocessor," Proc. IEEE Int'l Symp. VLSI Design, Automation and Test (VLSI-DAT 07), IEEE Press, 2007, pp. 1-4.
6. T.J. Foster, D.L. Lastor, and P. Singh, "First Silicon Functional Validation and Debug of Multicore Microprocessors," IEEE Trans. VLSI Systems, vol. 15, no. 5, 2007, pp. 495-504.
7. M. Tremblay and S. Chaudhry, "A Third Generation 65nm, 16-Core, 32-Thread +32 Scout Threads CMT SPARC Processor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 08), IEEE Press, 2008, pp. 3-4.
8. C.E. McDowell and D.P. Helmbold, "Debugging Concurrent Programs," ACM Computing Surveys, vol. 21, no. 4, 1989, pp. 594-622.
9. I. Robertson et al., "Testing High-Speed, Large Scale Implementation of SerDes I/Os on Chips Used in Throughput Computing Systems," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 992-999.
10. I. Parulkar et al., "DFX of a 3rd Generation, 16-Core/32-Thread UltraSPARC CMT Microprocessor," Proc. Int'l Test Conf. (ITC 08), IEEE CS Press, 2008, pp. 1-10.
11. J.M. Ludden et al., "Functional Verification of POWER4 Microprocessor and POWER4 Microprocessor Systems," IBM J. Research and Development, vol. 46, no. 1, 2002, pp. 53-76.
12. S. Hangal et al., "TSOTool: A Program for Verifying Memory Systems Using the Memory Consistency Model," Proc. 31st Ann. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 114-123.
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