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Comprehensive Approach to High-Performance Server Chipset Debug
May/June 2009 (vol. 26 no. 3)
pp. 70-77
Ishwar Parulkar, Sun Microsystems
Babu Turumella, Sun Microsystems

This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.

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Index Terms:
verification, test generation, design and test, multithreaded processors, server chipset, debug, SerDes, CMT Sparc microprocessor, RAS
Citation:
Ishwar Parulkar, Babu Turumella, "Comprehensive Approach to High-Performance Server Chipset Debug," IEEE Design & Test of Computers, vol. 26, no. 3, pp. 70-77, May-June 2009, doi:10.1109/MDT.2009.53
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