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Automating IEEE 1500 Core Test—An EDA Perspective
May/June 2009 (vol. 26 no. 3)
pp. 6-15
Krishna Chakravadhanula, Cadence Design Systems
Vivek Chickermane, Cadence Design Systems

Editor's note:

Standardized design and test practices enable automation. This article describes a methodology and corresponding tool set that combines automated support for IEEE Std 1500 and test data compression in one.

—Erik Jan Marinissen, IMEC

1. IEEE Std 1500, IEEE Standard for Embedded Core Test (SECT), IEEE, 2005; http://grouper.ieee.org/groups1500.
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8. T. Waayers, R. Morren, and R. Grandi, "Definition of a Robust Modular SOC Test Architecture; Resurrection of the Single TAM Daisy-Chain," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 610-619.
9. D. Appello et al., "On the Automation of the Test Flow of Complex SoCs," Proc. 24th VLSI Test Symp., IEEE CS Press, 2006, pp. 166-171.
10. C. Barnhart et al., "Extending OPMISR beyond 10x Scan Test Efficiency," IEEE Design &Test, vol. 19, no. 5, 2002, pp. 65-73.
11. I. Hamzaoglu and J.H. Patel, "Reducing Test Application Time for Full-Scan Embedded Cores," Proc. 29th Ann. Int'l Symp. Fault-Tolerant Computing, IEEE CS Press, 1999, pp. 260-267.
12. J. Rajski et al., "Embedded Deterministic Test for Low-Cost Manufacturing Test," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 301-310.

Index Terms:
IEEE Std 1500, core test, EDA, test data compression
Citation:
Krishna Chakravadhanula, Vivek Chickermane, "Automating IEEE 1500 Core Test—An EDA Perspective," IEEE Design & Test of Computers, vol. 26, no. 3, pp. 6-15, May-June 2009, doi:10.1109/MDT.2009.47
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