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Issue No.03 - May/June (2009 vol.26)
pp: 6-15
Krishna Chakravadhanula , Cadence Design Systems
Vivek Chickermane , Cadence Design Systems
ABSTRACT
<p>Editor's note:</p><p>Standardized design and test practices enable automation. This article describes a methodology and corresponding tool set that combines automated support for IEEE Std 1500 and test data compression in one.</p><p align="right"><it>—Erik Jan Marinissen, IMEC</it></p>
INDEX TERMS
IEEE Std 1500, core test, EDA, test data compression
CITATION
Krishna Chakravadhanula, Vivek Chickermane, "Automating IEEE 1500 Core Test—An EDA Perspective", IEEE Design & Test of Computers, vol.26, no. 3, pp. 6-15, May/June 2009, doi:10.1109/MDT.2009.47
REFERENCES
1. IEEE Std 1500, IEEE Standard for Embedded Core Test (SECT), IEEE, 2005; http://grouper.ieee.org/groups1500.
2. E.J. Marinissen, S.K. Goel, and M. Lousberg, "Wrapper Design for Embedded Core Test," Proc. Int'l Test Conf. (ITC 00), IEEE CS Press, 2000, pp. 911-920.
3. Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded-Core Based System Chips," Proc. Int'l Test Conf. (ITC 98), IEEE CS Press, 1998, pp. 130-143.
4. A. Sehgal et al., "IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 1203-1212.
5. H.J. Vermaak and H.G. Kerkhoff, "Enhanced P1500 Compliant Wrapper Suitable for Delay Fault Testing of Embedded Cores," Proc. 8th European Test Workshop, IEEE CS Press, 2003, pp. 121-126.
6. F. da Silva, T. McLaurin, and T. Waayers, The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500, Springer, 2006.
7. A. Benso et al., "IEEE Standard 1500 Compliance Verification for Embedded Cores," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 4, 2008, pp. 397-407.
8. T. Waayers, R. Morren, and R. Grandi, "Definition of a Robust Modular SOC Test Architecture; Resurrection of the Single TAM Daisy-Chain," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 610-619.
9. D. Appello et al., "On the Automation of the Test Flow of Complex SoCs," Proc. 24th VLSI Test Symp., IEEE CS Press, 2006, pp. 166-171.
10. C. Barnhart et al., "Extending OPMISR beyond 10x Scan Test Efficiency," IEEE Design &Test, vol. 19, no. 5, 2002, pp. 65-73.
11. I. Hamzaoglu and J.H. Patel, "Reducing Test Application Time for Full-Scan Embedded Cores," Proc. 29th Ann. Int'l Symp. Fault-Tolerant Computing, IEEE CS Press, 1999, pp. 260-267.
12. J. Rajski et al., "Embedded Deterministic Test for Low-Cost Manufacturing Test," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 301-310.
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