Issue No.02 - March/April (2009 vol.26)
Published by the IEEE Computer Society
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.26
Thermal Issues in the Nano-Tera CMOSAIC Project
Continuous technical advances are fueling the trend toward more sophisticated and high-performance chip designs, increasing functionality and clock rates while shrinking the feature sizes. Interconnects have not followed the same scaling curve as transistors, hence they have become a limiting factor in performance and power consumption.
One solution to the problem of the rising power consumption in interconnects is 3D stacking, which reduces the length of the communication lines through vertical integration of circuit blocks. However, 3D stacking substantially increases power density due to the placement of computational units on top of each other. High power densities are already a major concern in 2D circuits, and in 3D systems the problem is even more severe. The 3D stacked systems exacerbate temperature-induced problems, leading to degraded performance and reliability if not handled properly.
The CMOSAIC (3D Stacked Architectures with Interlayer Cooling) project is a genuine opportunity to contribute to the realization of arguably the most complicated system that mankind has ever assembled: a 3D stack of computer chips with a functionality per unit volume that nearly parallels the functional density of a human brain. CMOSAIC's aggressive goal is to provide the necessarily 3D integrated cooling system that is the key to compressing almost 1,012 nanometer-sized functional units (1 Tera) into one cubic centimeter with a 10- to 100-fold higher connectivity than otherwise possible. Even the most advanced air-cooling methods are inadequate for high-performance 3D integrated-circuit systems in which the main challenge is to remove the heat produced by multiple stacked dies in a 1-3 cm 3 volume, each layer dissipating 100-150 W/cm 2. State-of-the-art single-phase liquid and two-phase cooling systems, using specifically designed microchannel arrangements, and employing coolants ranging from liquid water and two-phase environmentally friendly refrigerants to novel engineered nanofluids offer significant advantages in addressing heat removal challenges leading to practical 3D systems. CMOSAIC aims at developing the engineering science base that will advance the state of the art in high-density electronics cooling.
Specifically, this project brings together internationally recognized experts of leading Swiss universities and industry (EPFL, ETH Zurich, and the IBM Research Laboratory in Rüschlikon) to thoroughly investigate this interdisciplinary problem at different levels (architecture, microfabrication, liquid cooling, two-phase cooling, nanofluids). These experts are joining forces to research the related physics and to develop the necessary thermal and electronic computational tools and methods. The project includes an intensive experimental program, consisting of challenging flow visualizations and heat transfer measurements in microchannel systems of hydraulic diameter that is often comparable to or smaller than that of a human hair, with complex fluids flowing through them. The project also targets the development of novel theoretical models explaining the physics and new electronics packing models together with new micromanufacturing processes. The verification of the proposed novel approaches resulting from this project will be conducted using several prototypes that will be built and tested. With respect to the Nano-Tera Swiss program proposal, this project addresses the vertical axis of micro- and nanoelectronics, particularly the aspect of system integration. The results of this project, as defined in the Nano-Tera Program, will be a significant step toward "achieving system complexities that are two-to-three orders of magnitude higher than today's state-of-the-art," by developing the fundamental understanding, methods, and tools required for efficient and reliable design of true 3D IC systems.
CMOSAIC is one of the most ambitious projects in the field of 3D chips, covering many different areas of research and targeting the goal at different abstraction levels. Only the joint work of research experts and industrial partners allows the pursuit of such interesting objectives. Please visit the following website for further information: http://www.nano-tera.ch/projects/67.php.
For more information, please contact Jose L. Ayala (email@example.com), Complutense University of Madrid.
IEEE Navigation Tool
IEEE is developing a new technology discovery and navigation system to enable professionals and researchers to find conferences, publications, and other resources that match their technical interests. In this regard, IEEE has identified 14 market sectors, and CEDA will join this initiative by providing tags for each sector in EDA, which will be stored in a global IEEE database. Also, there will be an automated process for mapping EDA-related conferences and publications to the different identified sectors.
The final objective of this initiative is to provide an interface for professionals that help them in finding connections between industry, research, and IEEE products and services. This new tool is complementary to other services already provided by the IEEE, such as Xplore, or external services from other entities, such as Google Search. The plan is to make this new IEEE Navigation Tool available to the public at the end of the first quarter of 2009, and CEDA is working on making this new tool accessible to EDA professionals directly from its website.
For further information, please contact David Atienza (firstname.lastname@example.org).
IEEE's 125th Anniversary
In 2009, the IEEE commemorates 125 years of fostering technological innovation and excellence for the public good. Although 13 May 2009 is the IEEE's official anniversary date, the "Engineering the Future" celebration will include a year full of activities, events, and the first IEEE Presidents' Change the World Competition for students. And, what is even more appealing, everyone can be a part of IEEE's Anniversary Celebration.
The schedule of planned activities for this 125th anniversary year is growing everyday with new proposals. Among others, these are some of the celebratory activities: the IEEE Presidents' Change the World Competition (where the winning submission will receive US $10,000 in June 2009 at the annual IEEE honors ceremony), the IEEE125.org (website that centralizes all the information about the 125th Anniversary activities), IEEE Engineering the Future Media Roundtable (media event scheduled for 10 March in New York), IEEE Global Engineering the Future Day (on 13 May 2009, IEEE's official anniversary) and the IEEE Global Engineering the Future Series (eight events planned all around the world: Austin, Bangalore, Tokyo, Beijing, Boston, London, Munich, and San Jose).
For further information, please visit http://www. ieee125.org.
IFIP WG 10.5, Design and Engineering of Electronic Systems
IFIP is the leading multinational, apolitical organization in information and communications technologies and sciences, recognized by the United Nations and other world bodies. It represents IT societies from 56 countries or regions, covering all five continents with a total membership of more than half a million; and it links more than 3,500 scientists from academia and industry, organized in more than 101 working groups reporting to 13 technical committees. The Working Group 10.5 "Design and Engineering of Electronic Systems" belongs to the IFIP Technical Committee 10. It was established in 1994 by merging the old 10.2 and 10.5 working groups.
The Working Group 10.5 aims to provide a forum among creative experts to explore problem areas and solutions for the design of complex electronic systems and also to disseminate the solutions to a broader industrial and educational sphere. The working group targets a broad range of topics related to the design and engineering of heterogeneous systems, containing hardware, software, and mechanical parts. In summary, its main areas of interest include these: system design methods, embedded systems, modeling and specification, design validation, reconfigurable computing, VLSI systems and applications, power-aware design, analog and mixed-signal systems, and fundamental CAD algorithms, among others.
The next meeting of the IFIP WG 10.5 will take place in Nice, France, during the DATE 2009 conference. For more information, please visit the WG website: http://www.inf.ufrgs.br/ifip10-5/index.html.
Upcoming CEDA Events
CEDA conferences provide excellent opportunities for those interested in learning about the latest technical trends in electronic design and automation. If you'd like to participate or you have an idea about new topics of interest for our conferences, please contact William Joyner (email@example.com), CEDA vice president of conferences.
7th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)
13–15 July 2009
46th Design Automation Conference (DAC)
26–31 July 2009
9th International Forum on Application-Specific Multiprocessor SoC (MPSoC)
2–7 August 2009
19th International Workshop on Power and Timing Modeling, Optimization, and Simulation (PATMOS)
9–11 September 2009