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Issue No.02 - March/April (2009 vol.26)
pp: 64-73
Li-Ming Denq , National Tsing Hua University
Yu-Tsao Hsing , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
ABSTRACT
<p>Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.</p>
INDEX TERMS
routing penalty, at-speed testing, hybrid BIST, diagnostic syndrome, failure bitmap, yield enhancement, MECA system, routing-area overhead
CITATION
Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu, "Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories", IEEE Design & Test of Computers, vol.26, no. 2, pp. 64-73, March/April 2009, doi:10.1109/MDT.2009.37
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