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| Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu, "Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories," IEEE Design & Test of Computers, vol. 26, no. 2, pp. 64-73, March/April, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2009.37, author = {Li-Ming Denq and Yu-Tsao Hsing and Cheng-Wen Wu}, title = {Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories}, journal ={IEEE Design & Test of Computers}, volume = {26}, number = {2}, issn = {0740-7475}, year = {2009}, pages = {64-73}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.37}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories IS - 2 SN - 0740-7475 SP64 EP73 EPD - 64-73 A1 - Li-Ming Denq, A1 - Yu-Tsao Hsing, A1 - Cheng-Wen Wu, PY - 2009 KW - routing penalty KW - at-speed testing KW - hybrid BIST KW - diagnostic syndrome KW - failure bitmap KW - yield enhancement KW - MECA system KW - routing-area overhead VL - 26 JA - IEEE Design & Test of Computers ER - | |||
Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.
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