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Issue No.02 - March/April (2009 vol.26)
pp: 52-63
Dimitris Gizopoulos , University of Piraeus
Mihalis Psarakis , University of Piraeus
Danilo Ravotto , Politecnico di Torino
Andreas Apostolakis , University of Piraeus
<p>Testing communication peripherals in an environment of systems on a chip is particularly challenging. The authors explore two test program generation approaches&#x2014;one fully automated and one deterministically guided&#x2014;and propose a novel combination of the two schemes that can be applied in a generic manner on a wide set of communication cores.</p>
Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Andreas Apostolakis, "Test Program Generation for Communication Peripherals in Processor-Based SoC Devices", IEEE Design & Test of Computers, vol.26, no. 2, pp. 52-63, March/April 2009, doi:10.1109/MDT.2009.43
1. G. Hetherington et al., "Logic BIST for Large Industrial Designs: Real Issues and Case Studies," Proc. IEEE Int'l Test Conf. (ITC 99), IEEE CS Press, 1999, pp. 358-367.
2. A. Krstic et al., "Embedded Software-Based Self-Test for Programmable Core-Based Designs," IEEE Design &Test, vol. 19, no. 4, 2002, pp. 18-27.
3. A. Paschalis and D. Gizopoulos, "Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, 2005, pp. 88-99.
4. F. Corno et al., "On the Test of Microprocessor IP Cores," Proc. Design Automation &Test in Europe (DATE 01), IEEE Press, 2001, pp. 209-213.
5. P. Parvathala, K. Maneparambil, and W. Lindsay, "FRITS—A Microprocessor Functional BIST Method," Proc. IEEE Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 590-598.
6. I. Bayraktaroglu, J. Hunt, and D. Watkins, "Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues," Proc. IEEE Int'l Test. Conf. (ITC 06), IEEE CS Press, art. 297675 (7 pp.).
7. K. Jayaraman, V.M. Vedula, and J.A. Abraham, "Native Mode Functional Self-Test Generation for Systems-on-Chip," Proc. Int'l Symp. Quality Electronic Design (ISQED 02), IEEE CS Press, 2002, pp. 280-285.
8. S. Hwang and J.A. Abraham, "Reuse of Addressable System Bus for SoC Testing," Proc. IEEE Int'l ASIC/SoC Conf., IEEE Press, 2001, pp. 215-219.
9. J.-R. Huang, M.K. Iyer, and K.-T. Cheng, "A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs," Proc. IEEE VLSI Test Symp. (VTS 01), IEEE CS Press, 2001, pp. 198-203.
10. W.-C. Lai and K.-T. Cheng, "Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip," Proc. IEEE/ACM Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 59-64.
11. L. Bolzani et al., "An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores," Proc. IEEE Int'l On-Line Testing Symp. (IOLTS 07), IEEE CS Press, 2007, pp. 265-270.
12. A. Apostolakis et al., "Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 8, 2007, pp. 971-975.
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