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| ASCII Text | x | ||
| Wei Zhang, "Computing and Minimizing Cache Vulnerability to Transient Errors," IEEE Design & Test of Computers, vol. 26, no. 2, pp. 44-51, March/April, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2009.29, author = {Wei Zhang}, title = {Computing and Minimizing Cache Vulnerability to Transient Errors}, journal ={IEEE Design & Test of Computers}, volume = {26}, number = {2}, issn = {0740-7475}, year = {2009}, pages = {44-51}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.29}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Computing and Minimizing Cache Vulnerability to Transient Errors IS - 2 SN - 0740-7475 SP44 EP51 EPD - 44-51 A1 - Wei Zhang, PY - 2009 VL - 26 JA - IEEE Design & Test of Computers ER - | |||
Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.
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