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Computing and Minimizing Cache Vulnerability to Transient Errors
March/April 2009 (vol. 26 no. 2)
pp. 44-51
Wei Zhang, Southern Illinois University Carbondale

Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.

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Wei Zhang, "Computing and Minimizing Cache Vulnerability to Transient Errors," IEEE Design & Test of Computers, vol. 26, no. 2, pp. 44-51, March-April 2009, doi:10.1109/MDT.2009.29
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