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Issue No.02 - March/April (2009 vol.26)
pp: 44-51
Wei Zhang , Southern Illinois University Carbondale
ABSTRACT
<p>Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.</p>
CITATION
Wei Zhang, "Computing and Minimizing Cache Vulnerability to Transient Errors", IEEE Design & Test of Computers, vol.26, no. 2, pp. 44-51, March/April 2009, doi:10.1109/MDT.2009.29
REFERENCES
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2. S.S. Mukherjee, J. Emer, and S.K. Reinhardt, "The Soft Error Problem: An Architectural Perspective," Proc. 11th Int'l Symp. High-Performance Computer Architecture (HPCA 05), IEEE CS Press, 2005, pp. 243-247.
3. S. Kaxiras, Z. Hu, and M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power," Proc. 28th Int'l Symp. Computer Architecture (ISCA 01), IEEE CS Press, 2001, pp. 240-251.
4. T. Sherwood et al., "Automatically Characterizing Large Scale Program Behavior," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 45-57.
5. H.S. Lee et al., "Eager Writeback: A Technique for Improving Bandwidth Utilization," Proc. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 00), IEEE CS Press, 2000, pp. 11-21.
6. L. Li et al., "Soft Error and Energy Consumption Interactions: A Data Cache Perspective," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED 04), IEEE CS Press, 2004, pp. 132-137.
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