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March/April 2009 (vol. 26 no. 2)
pp. 4-4

Risks are notably increasing in the design of complex SoCs at the 65-nm technology node and beyond. Escalating design costs, increasing profitability and time-to-market pressures, and skyrocketing power consumption—in conjunction with a lower first-silicon success rate, and lower chip manufacturability and reliability—are among the key challenges that chip makers are confronting. To minimize the risks in the face of these challenges requires skillful management of the design process, which has become a core competency of leading chip makers. This issue of Design & Test features a special issue on the management of emerging SoC development. The special issue consists of four articles, contributed by experienced design managers from leading semiconductor companies. In addition, four general-interest articles address diverse design and test issues.

Index Terms:
design and test, SoC development, design challenges, design management
"Managing design and test challenges," IEEE Design & Test of Computers, vol. 26, no. 2, pp. 4-4, March-April 2009, doi:10.1109/MDT.2009.40
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