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A CMOS Resizing Methodology for Analog Circuits
January/February 2009 (vol. 26 no. 1)
pp. 78-87
ASCII Text
x 
 
Timothée Levi, Jean Tomas, Noëlle Lewis, Pascal Fouillat, "A CMOS Resizing Methodology for Analog Circuits," IEEE Design & Test of Computers, vol. 26, no. 1, pp. 78-87, January/February, 2009.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2009.1,
author = {Timothée Levi and Jean Tomas and Noëlle Lewis and Pascal Fouillat},
title = {A CMOS Resizing Methodology for Analog Circuits},
journal ={IEEE Design & Test of Computers},
volume = {26},
number = {1},
issn = {0740-7475},
year = {2009},
pages = {78-87},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.1},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - A CMOS Resizing Methodology for Analog Circuits
IS - 1
SN - 0740-7475
SP78
EP87
EPD - 78-87
A1 - Timothée Levi,
A1 - Jean Tomas,
A1 - Noëlle Lewis,
A1 - Pascal Fouillat,
PY - 2009
KW - analog design
KW - design reuse
KW - MOS technology
KW - resizing methodology
KW - technology migration
VL - 26
JA - IEEE Design & Test of Computers
ER -
 
Timothée Levi, LIMMS, University of Tokyo
Jean Tomas, Bordeaux University
Noëlle Lewis, Bordeaux University
Pascal Fouillat, Ecole Nationale Supérieure d'Electronique de Bordeaux
This article presents a CMOS resizing methodology for analog circuits during a technology migration, with easy-to-apply scaling rules based on a simple MOS transistor model. The goals are to transpose a circuit topology from one technology to another while preserving the main figures of merit and to quickly calculate the new transistor dimensions.

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Index Terms:
analog design, design reuse, MOS technology, resizing methodology, technology migration
Citation:
Timothée Levi, Jean Tomas, Noëlle Lewis, Pascal Fouillat, "A CMOS Resizing Methodology for Analog Circuits," IEEE Design & Test of Computers, vol. 26, no. 1, pp. 78-87, Jan.-Feb. 2009, doi:10.1109/MDT.2009.1
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