The Community for Technology Leaders
RSS Icon
Issue No.01 - January/February (2009 vol.26)
pp: 68-77
Wenjing Rao , University of Illinois at Chicago
Alex Orailoglu , University of California, San Diego
Ramesh Karri , Polytechnic University of NYU
This article presents a mathematical model and algorithm that address the problem of logic function mapping in a nanoelectronic environment. Enhancement techniques improve the algorithm's runtime by significantly cutting down on unnecessary backtracking processes.
nanoelectronic system, crossbar, defect tolerance, reliability, logic synthesis, bipartite graph, logic function mapping, two-level logic, nanofabric
Wenjing Rao, Alex Orailoglu, Ramesh Karri, "Logic Mapping in Crossbar-Based Nanoarchitectures", IEEE Design & Test of Computers, vol.26, no. 1, pp. 68-77, January/February 2009, doi:10.1109/MDT.2009.14
1. International Technology Roadmap for Semiconductors—Emerging Research Devices, Semiconductor Industry Assoc., 2006.
2. V.V. Zhirnov and D.J.C. Herr, "New Frontiers: Self-Assembly and Nanoelectronics," Computer, vol. 34, no. 1, Jan. 2001, pp. 34-43.
3. P.J. Kuekes, D.R. Stewart, and R.S. Williams, "The Crossbar Latch: Logic Value Storage, Restoration, and Inversion in Crossbar Circuits," J. Applied Physics, vol. 97, no. 3, Feb. 2005, http://scitation.
4. A. DeHon, "Nanowire-Based Programmable Architectures," ACM J. Emerging Technologies in Computing Systems, vol. 1, no. 2, July 2005, pp. 109-162.
5. C.P. Collier et al., "Electronically Configurable Molecular-Based Logic Gates," Science, vol. 285, no. 5426, 16 July 1999, pp. 391-394.
6. G. Snider, P.J. Kuekes, and R.S. Williams, "CMOS-Like Logic in Defective, Nanoscale Crossbars," Nanotechnology, vol. 15, no. 8, Aug. 2004, pp. 881-891.
7. S.C. Goldstein and M. Budiu, "NanoFabrics: Spatial Computing Using Molecular Electronics," Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA 01), IEEE CS Press, 2001, pp. 178-191.
8. D.B. Strukov and K.K. Likharev, "CMOL FPGA: A Reconfigurable Architecture for Hybrid Digital Circuits with Two-Terminal Nanodevices," Nanotechnology, vol. 16, no. 6, June 2005, pp. 888-900.
9. A. DeHon and H. Naeimi, "Seven Strategies for Tolerating Highly Defective Fabrication," IEEE Design &Test, vol. 22, no. 4, July-Aug. 2005, pp. 306-315.
10. C.-L. Wey, "Fault Location in Repairable Programmable Logic Arrays," Proc. Int'l Test Conf. (ITC 89), IEEE Press, 1989, pp. 679-685.
11. Collaborative Benchmarking Laboratory, 1993 LGSynth Benchmarks, North Carolina State Univ., Dept. of Computer Science, 1993.
17 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool