Issue No.01 - January/February (2009 vol.26)
Lucía Costas-Pérez , University of Vigo
Juan J. Rodríguez-Andina , University of Vigo
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2009.6
Fault tolerance capabilities are becoming a fundamental requirement in many designs. Improving these systems' dependability under demanding environmental and operating conditions requires new techniques that use concurrent error detection (CED) strategies to guarantee data integrity. The system-level algorithmic CED methodology uses selective redundancy for online monitoring of system-level properties, without requiring any modifications to the target system.
dependability, concurrent error detection, system-level error detection, digital-signal processing, wavelet transform, CED
Lucía Costas-Pérez, Juan J. Rodríguez-Andina, "Algorithmic Concurrent Error Detection in Complex Digital-Processing Systems", IEEE Design & Test of Computers, vol.26, no. 1, pp. 60-67, January/February 2009, doi:10.1109/MDT.2009.6