The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.01 - January/February (2009 vol.26)
pp: 26-35
Laung-Terng Wang , SynTest Technologies
Ravi Apte , SynTest Technologies
Shianling Wu , SynTest Technologies
Boryau Sheu , SynTest Technologies
Kuen-Jong Lee , National Cheng Kung University
Xiaoqing Wen , Kyushu Institute of Technology
Wen-Ben Jone , University of Cincinnati
Jianghao Guo , University of Cincinnati
Wei-Shin Wang , Silicon Integrated Systems
Hao-Jan Chao , SynTest Technologies
Jinsong Liu , SynTest Technologies
Yanlong Niu , SynTest Technologies
Yi-Chih Sung , SynTest Technologies
Chi-Chun Wang , SynTest Technologies
Fangfang Li , SynTest Technologies
ABSTRACT
Tool support is crucial in widespread adoption of a standard. This article describes a set of tools and associated flow for DFT insertion and test generation based on IEEE Std 1500.
INDEX TERMS
Turbo1500, core-based testing, core diagnosis, IEEE Std 1500, hierarchical testing, SoC testing
CITATION
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Jianghao Guo, Wei-Shin Wang, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li, "Turbo1500: Core-Based Design for Test and Diagnosis", IEEE Design & Test of Computers, vol.26, no. 1, pp. 26-35, January/February 2009, doi:10.1109/MDT.2009.21
REFERENCES
1. L.-T. Wang, C.-W. Wu, and X. Wen eds., , VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.
2. Y. Zorian and A. Yessayan, "IEEE 1500 Utilization in SoC Test and Design," Proc. IEEE Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 1203-1212.
3. IEEE Std 1500-2005, IEEE Standard for Embedded Core Test, IEEE, 2005.
4. L.-T. Wang et al., "Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard," Proc. Int'l Test Conf. (ITC 08), IEEE CS Press, 2008, paper 29.3.
5. IEEE Std 1450.6-2001, Core Test Language, IEEE, 2001.
6. E. Marinissen et al., "On IEEE P1500's Standard for Embedded Core Test," J. Electronic Testing: Theory and Applications, vol. 18, nos. 4-5, Aug. 2002, Springer Netherlands, pp. 365-383.
7. C. Liu, K. Chakrabarty, and W.-B. Jone, "System/Network-on-Chip Test Architectures," System-on-Chip Test Architectures: Nanometer Design for Testability, L.-T. Wang, C.E. Stroud, and N.A. Touba eds., Morgan Kaufmann, 2007, pp. 171-224.
8. L.-T. Wang et al., , "VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG," IEEE Design &Test, vol. 25, no. 2, Mar./Apr. 2008, pp. 122-130.
9. R. Kapur, S. Mitra, and T.W. Williams, "Historical Perspective on Scan Compression," IEEE Design &Test, vol. 25, no. 2, Mar./Apr. 2008, pp. 114-120.
10. T. M. Mak and S. Venkataraman, "Design for Debug and Diagnosis," System-on-Chip Test Architectures: Nanometer Design for Testability, L.-T. Wang, C.E. Stroud, and N.A. Touba eds., Morgan Kaufmann, 2007, pp. 463-504.
11. K.-L. Cheng et al., , "An SoC Test Integration Platform and Its Industrial Realization," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 1213-1222.
12. IEEE P1687-2007 Proposal, IEEE Internal Boundary-Scan Proposal for Embedded Test and Debug, IEEE, 2007.
30 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool